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1. Intel FPGA Integer Arithmetic IP Cores
2. LPM_COUNTER (Counter) IP Core
3. LPM_DIVIDE (Divider) Intel FPGA IP Core
4. LPM_MULT (Multiplier) IP Core
5. LPM_ADD_SUB (Adder/Subtractor)
6. LPM_COMPARE (Comparator)
7. ALTECC (Error Correction Code: Encoder/Decoder) IP Core
8. Intel FPGA Multiply Adder IP Core
9. ALTMEMMULT (Memory-based Constant Coefficient Multiplier) IP Core
10. ALTMULT_ACCUM (Multiply-Accumulate) IP Core
11. ALTMULT_ADD (Multiply-Adder) IP Core
12. ALTMULT_COMPLEX (Complex Multiplier) IP Core
13. ALTSQRT (Integer Square Root) IP Core
14. PARALLEL_ADD (Parallel Adder) IP Core
15. Integer Arithmetic IP Cores User Guide Document Archives
16. Document Revision History for Intel FPGA Integer Arithmetic IP Cores User Guide
7.1. ALTECC Encoder Features
7.2. Verilog HDL Prototype (ALTECC_ENCODER)
7.3. Verilog HDL Prototype (ALTECC_DECODER)
7.4. VHDL Component Declaration (ALTECC_ENCODER)
7.5. VHDL Component Declaration (ALTECC_DECODER)
7.6. VHDL LIBRARY_USE Declaration
7.7. Encoder Ports
7.8. Decoder Ports
7.9. Encoder Parameters
7.10. Decoder Parameters
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4.7.2. General 2 Tab
Parameter | Value | Default Value | Description |
---|---|---|---|
Datab Input | |||
Does the 'datab' input bus have a constant value? | No Yes |
No | Select Yes to specify the constant value of the ‘datab’ input bus, if any. |
Value | Any value greater than 0 | 0 | Specify the constant value of datab[] port. |
Multiplication Type | |||
Which type of multiplication do you want? | Unsigned Signed |
Unsigned | Specify the representation format for both dataa[] and datab[] inputs. |
Implementation Style | |||
Which multiplier implementation should be used? | Use the default implementation Use the dedicated multiplier circuitry Use logic elements |
Use the default implementation | Select the desired method to determine the width of the result[] port. |