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1. Intel FPGA Integer Arithmetic IP Cores
2. LPM_COUNTER (Counter) IP Core
3. LPM_DIVIDE (Divider) Intel FPGA IP Core
4. LPM_MULT (Multiplier) IP Core
5. LPM_ADD_SUB (Adder/Subtractor)
6. LPM_COMPARE (Comparator)
7. ALTECC (Error Correction Code: Encoder/Decoder) IP Core
8. Intel FPGA Multiply Adder IP Core
9. ALTMEMMULT (Memory-based Constant Coefficient Multiplier) IP Core
10. ALTMULT_ACCUM (Multiply-Accumulate) IP Core
11. ALTMULT_ADD (Multiply-Adder) IP Core
12. ALTMULT_COMPLEX (Complex Multiplier) IP Core
13. ALTSQRT (Integer Square Root) IP Core
14. PARALLEL_ADD (Parallel Adder) IP Core
15. Integer Arithmetic IP Cores User Guide Document Archives
16. Document Revision History for Intel FPGA Integer Arithmetic IP Cores User Guide
7.1. ALTECC Encoder Features
7.2. Verilog HDL Prototype (ALTECC_ENCODER)
7.3. Verilog HDL Prototype (ALTECC_DECODER)
7.4. VHDL Component Declaration (ALTECC_ENCODER)
7.5. VHDL Component Declaration (ALTECC_DECODER)
7.6. VHDL LIBRARY_USE Declaration
7.7. Encoder Ports
7.8. Decoder Ports
7.9. Encoder Parameters
7.10. Decoder Parameters
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3.5. Ports
The following tables list the input and output ports for the LPM_DIVIDE IP core.
Port Name | Required | Description |
---|---|---|
numer[] | Yes | Numerator data input. The size of the input port depends on the LPM_WIDTHN parameter value. |
denom[] | Yes | Denominator data input. The size of the input port depends on the LPM_WIDTHD parameter value. |
clock | No | Clock input for pipelined usage. For LPM_PIPELINE values other than 0 (default), the clock port must be enabled. |
clken | No | Clock enable pipelined usage. When the clken port is asserted high, the division operation takes place. When the signal is low, no operation occurs. If omitted, the default value is 1. |
aclr | No | Asynchronous clear port used at any time to reset the pipeline to all '0's asynchronously to the clock input. |
Port Name | Required | Description |
---|---|---|
quotient[] | Yes | Data output. The size of the output port depends on the LPM_WIDTHN parameter value. |
remain[] | Yes | Data output. The size of the output port depends on the LPM_WIDTHD parameter value. |