Visible to Intel only — GUID: kly1463120429632
Ixiasoft
Visible to Intel only — GUID: kly1463120429632
Ixiasoft
8.6.7. Pipelining Tab
Parameter | IP Generated Parameter | Value | Default Value | Description |
---|---|---|---|---|
Pipelining Configuration | ||||
Do you want to add pipeline register to the input? | gui_pipelining | No, Yes |
No | Select Yes to enable an additional level of pipeline register to the input signals. You must specify a value greater than 0 for Please specify the number of latency clock cycles parameter. |
Please specify the number of latency clock cycles | latency | Any value greater than 0 | 0 | Specifies the desired latency in clock cycles. One level of pipeline register = 1 latency in clock cycle. You must select YES for Do you want to add pipeline register to the input? to enable this option. |
What is the source for clock input? | gui_input_latency_clock | CLOCK0, CLOCK1, CLOCK2 |
CLOCK0 | Select Clock0 , Clock1 or Clock2 to enable and specify the pipeline register input clock signal. You must select YES for Do you want to add pipeline register to the input? to enable this option. |
What is the source for asynchronous clear input? | gui_input_latency_aclr | NONE ACLR0 ACLR1 |
NONE | Specifies the register asynchronous clear source for the additional pipeline register. You must select YES for Do you want to add pipeline register to the input? to enable this option. |
What is the source for synchronous clear input? | gui_input_latency_sclr | NONE SCLR0 SCLR1 |
NONE | Specifies the register synchronous clear source for the additional pipeline register. You must select YES for Do you want to add pipeline register to the input? to enable this option. |