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1. Intel FPGA Integer Arithmetic IP Cores
2. LPM_COUNTER (Counter) IP Core
3. LPM_DIVIDE (Divider) Intel FPGA IP Core
4. LPM_MULT (Multiplier) IP Core
5. LPM_ADD_SUB (Adder/Subtractor)
6. LPM_COMPARE (Comparator)
7. ALTECC (Error Correction Code: Encoder/Decoder) IP Core
8. Intel FPGA Multiply Adder IP Core
9. ALTMEMMULT (Memory-based Constant Coefficient Multiplier) IP Core
10. ALTMULT_ACCUM (Multiply-Accumulate) IP Core
11. ALTMULT_ADD (Multiply-Adder) IP Core
12. ALTMULT_COMPLEX (Complex Multiplier) IP Core
13. ALTSQRT (Integer Square Root) IP Core
14. PARALLEL_ADD (Parallel Adder) IP Core
15. Integer Arithmetic IP Cores User Guide Document Archives
16. Document Revision History for Intel FPGA Integer Arithmetic IP Cores User Guide
7.1. ALTECC Encoder Features
7.2. Verilog HDL Prototype (ALTECC_ENCODER)
7.3. Verilog HDL Prototype (ALTECC_DECODER)
7.4. VHDL Component Declaration (ALTECC_ENCODER)
7.5. VHDL Component Declaration (ALTECC_DECODER)
7.6. VHDL LIBRARY_USE Declaration
7.7. Encoder Ports
7.8. Decoder Ports
7.9. Encoder Parameters
7.10. Decoder Parameters
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13.5. Ports
The following tables list the input and output ports for the ALTSQRT IP core.
Port Name | Required | Description |
---|---|---|
radical[] | Yes | Data input port. The size of the input port depends on the WIDTH parameter value. |
ena | No | Active high clock enable input port. |
clk | No | Clock input port that provides pipelined operation for the ALTSQRT IP core. For the values of PIPELINE parameter other than 0 (default value), the clock port must be connected. |
aclr | No | Asynchronous clear input port. that can be used at any time to reset the pipeline to all 0s, asynchronously to the clock signal. |
Port Name | Required | Description |
---|---|---|
remainder[] | Yes | The square root of the radical. The size of the remainder[] port depends on the R_PORT_WIDTH parameter value. |
q[] | Yes | Data output. The size of the q[] port depends on the Q_PORT_WIDTH parameter value. |