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1. Intel FPGA Integer Arithmetic IP Cores
2. LPM_COUNTER (Counter) IP Core
3. LPM_DIVIDE (Divider) Intel FPGA IP Core
4. LPM_MULT (Multiplier) IP Core
5. LPM_ADD_SUB (Adder/Subtractor)
6. LPM_COMPARE (Comparator)
7. ALTECC (Error Correction Code: Encoder/Decoder) IP Core
8. Intel FPGA Multiply Adder IP Core
9. ALTMEMMULT (Memory-based Constant Coefficient Multiplier) IP Core
10. ALTMULT_ACCUM (Multiply-Accumulate) IP Core
11. ALTMULT_ADD (Multiply-Adder) IP Core
12. ALTMULT_COMPLEX (Complex Multiplier) IP Core
13. ALTSQRT (Integer Square Root) IP Core
14. PARALLEL_ADD (Parallel Adder) IP Core
15. Integer Arithmetic IP Cores User Guide Document Archives
16. Document Revision History for Intel FPGA Integer Arithmetic IP Cores User Guide
7.1. ALTECC Encoder Features
7.2. Verilog HDL Prototype (ALTECC_ENCODER)
7.3. Verilog HDL Prototype (ALTECC_DECODER)
7.4. VHDL Component Declaration (ALTECC_ENCODER)
7.5. VHDL Component Declaration (ALTECC_DECODER)
7.6. VHDL LIBRARY_USE Declaration
7.7. Encoder Ports
7.8. Decoder Ports
7.9. Encoder Parameters
7.10. Decoder Parameters
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9.4. Ports
The following tables list the input and output ports for the ALTMEMMULT IP core.
Port Name | Required | Description |
---|---|---|
clock | Yes | Clock input to the multiplier. |
coeff_in[] | No | Coefficient input port for the multiplier. The size of the input port depends on the WIDTH_C parameter value. |
data_in[] | Yes | Data input port to the multiplier. The size of the input port depends on the WIDTH_D parameter value. |
sclr | No | Synchronous clear input. If unused, the default value is active high. |
sel[] | No | Fixed coefficient selection. The size of the input port depends on the WIDTH_S parameter value. |
sload_coeff | No | Synchronous load coefficient input port. Replaces the current selected coefficient value with the value specified in the coeff_in input. |
sload_data | No | Synchronous load data input port. Signal that specifies new multiplication operation and cancels any existing multiplication operation. If the MAX_CLOCK_CYCLES_PER_RESULT parameter has a value of 1, the sload_data input port is ignored. |
Port Name | Required | Description |
---|---|---|
result[] | Yes | Multiplier output port. The size of the input port depends on the WIDTH_R parameter value. |
result_valid | Yes | Indicates when the output is the valid result of a complete multiplication. If the MAX_CLOCK_CYCLES_PER_RESULT parameter has a value of 1, the result_valid output port is not used. |
load_done | No | Indicates when the new coefficient has finished loading. The load_done signal asserts when a new coefficient has finished loading. Unless the load_done signal is high, no other coefficient value can be loaded into the memory. |