Intel FPGA Integer Arithmetic IP Cores User Guide

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ID 683490
Date 10/05/2020
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Document Table of Contents
Document Table of Contents x
1. Intel FPGA Integer Arithmetic IP Cores 2. LPM_COUNTER (Counter) IP Core 3. LPM_DIVIDE (Divider) Intel FPGA IP Core 4. LPM_MULT (Multiplier) IP Core 5. LPM_ADD_SUB (Adder/Subtractor) 6. LPM_COMPARE (Comparator) 7. ALTECC (Error Correction Code: Encoder/Decoder) IP Core 8. Intel FPGA Multiply Adder IP Core 9. ALTMEMMULT (Memory-based Constant Coefficient Multiplier) IP Core 10. ALTMULT_ACCUM (Multiply-Accumulate) IP Core 11. ALTMULT_ADD (Multiply-Adder) IP Core 12. ALTMULT_COMPLEX (Complex Multiplier) IP Core 13. ALTSQRT (Integer Square Root) IP Core 14. PARALLEL_ADD (Parallel Adder) IP Core 15. Integer Arithmetic IP Cores User Guide Document Archives 16. Document Revision History for Intel FPGA Integer Arithmetic IP Cores User Guide
2. LPM_COUNTER (Counter) IP Core x
2.1. Features 2.2. Verilog HDL Prototype 2.3. VHDL Component Declaration 2.4. VHDL LIBRARY_USE Declaration 2.5. Ports 2.6. Parameters
3. LPM_DIVIDE (Divider) Intel FPGA IP Core x
3.1. Features 3.2. Verilog HDL Prototype 3.3. VHDL Component Declaration 3.4. VHDL LIBRARY_USE Declaration 3.5. Ports 3.6. Parameters
4. LPM_MULT (Multiplier) IP Core x
4.1. Features 4.2. Verilog HDL Prototype 4.3. VHDL Component Declaration 4.4. VHDL LIBRARY_USE Declaration 4.5. Signals 4.6. Parameters for Stratix V, Arria V, Cyclone V, and Intel® Cyclone® 10 LP Devices 4.7. Parameters for Intel® Stratix® 10, Intel® Arria® 10, and Intel® Cyclone® 10 GX Devices
4.6. Parameters for Stratix V, Arria V, Cyclone V, and Intel® Cyclone® 10 LP Devices x
4.6.1. General Tab 4.6.2. General 2 Tab 4.6.3. Pipelining Tab
4.7. Parameters for Intel® Stratix® 10, Intel® Arria® 10, and Intel® Cyclone® 10 GX Devices x
4.7.1. General Tab 4.7.2. General 2 Tab 4.7.3. Pipelining
5. LPM_ADD_SUB (Adder/Subtractor) x
5.1. Features 5.2. Verilog HDL Prototype 5.3. VHDL Component Declaration 5.4. VHDL LIBRARY_USE Declaration 5.5. Ports 5.6. Parameters
6. LPM_COMPARE (Comparator) x
6.1. Features 6.2. Verilog HDL Prototype 6.3. VHDL Component Declaration 6.4. VHDL LIBRARY_USE Declaration 6.5. Ports 6.6. Parameters
7. ALTECC (Error Correction Code: Encoder/Decoder) IP Core x
7.1. ALTECC Encoder Features 7.2. Verilog HDL Prototype (ALTECC_ENCODER) 7.3. Verilog HDL Prototype (ALTECC_DECODER) 7.4. VHDL Component Declaration (ALTECC_ENCODER) 7.5. VHDL Component Declaration (ALTECC_DECODER) 7.6. VHDL LIBRARY_USE Declaration 7.7. Encoder Ports 7.8. Decoder Ports 7.9. Encoder Parameters 7.10. Decoder Parameters
8. Intel FPGA Multiply Adder IP Core x
8.1. Features 8.2. Verilog HDL Prototype 8.3. VHDL Component Declaration 8.4. VHDL LIBRARY_USE Declaration 8.5. Signals 8.6. Parameters
8.1. Features x
8.1.1. Pre-adder 8.1.2. Systolic Delay Register 8.1.3. Pre-load Constant 8.1.4. Double Accumulator
8.1.1. Pre-adder x
8.1.1.1. Pre-adder Simple Mode 8.1.1.2. Pre-adder Coefficient Mode 8.1.1.3. Pre-adder Input Mode 8.1.1.4. Pre-adder Square Mode 8.1.1.5. Pre-adder Constant Mode
8.6. Parameters x
8.6.1. General Tab 8.6.2. Extra Modes Tab 8.6.3. Multipliers Tab 8.6.4. Preadder Tab 8.6.5. Accumulator Tab 8.6.6. Systolic/Chainout Tab 8.6.7. Pipelining Tab
9. ALTMEMMULT (Memory-based Constant Coefficient Multiplier) IP Core x
9.1. Features 9.2. Verilog HDL Prototype 9.3. VHDL Component Declaration 9.4. Ports 9.5. Parameters
10. ALTMULT_ACCUM (Multiply-Accumulate) IP Core x
10.1. Features 10.2. Verilog HDL Prototype 10.3. VHDL Component Declaration 10.4. VHDL LIBRARY_USE Declaration 10.5. Ports 10.6. Parameters
11. ALTMULT_ADD (Multiply-Adder) IP Core x
11.1. Features 11.2. Verilog HDL Prototype 11.3. VHDL Component Declaration 11.4. VHDL LIBRARY_USE Declaration 11.5. Ports 11.6. Parameters
12. ALTMULT_COMPLEX (Complex Multiplier) IP Core x
12.1. Complex Multiplication 12.2. Canonical Representation 12.3. Conventional Representation 12.4. Features 12.5. Verilog HDL Prototype 12.6. VHDL Component Declaration 12.7. VHDL LIBRARY_USE Declaration 12.8. Signals 12.9. Parameters
13. ALTSQRT (Integer Square Root) IP Core x
13.1. Features 13.2. Verilog HDL Prototype 13.3. VHDL Component Declaration 13.4. VHDL LIBRARY_USE Declaration 13.5. Ports 13.6. Parameters
14. PARALLEL_ADD (Parallel Adder) IP Core x
14.1. Feature 14.2. Verilog HDL Prototype 14.3. VHDL Component Declaration 14.4. VHDL LIBRARY_USE Declaration 14.5. Ports 14.6. Parameters
1. Intel FPGA Integer Arithmetic IP Cores
2. LPM_COUNTER (Counter) IP Core
3. LPM_DIVIDE (Divider) Intel FPGA IP Core
4. LPM_MULT (Multiplier) IP Core
5. LPM_ADD_SUB (Adder/Subtractor)
6. LPM_COMPARE (Comparator)
7. ALTECC (Error Correction Code: Encoder/Decoder) IP Core
8. Intel FPGA Multiply Adder IP Core
9. ALTMEMMULT (Memory-based Constant Coefficient Multiplier) IP Core
10. ALTMULT_ACCUM (Multiply-Accumulate) IP Core
11. ALTMULT_ADD (Multiply-Adder) IP Core
12. ALTMULT_COMPLEX (Complex Multiplier) IP Core
13. ALTSQRT (Integer Square Root) IP Core
14. PARALLEL_ADD (Parallel Adder) IP Core
15. Integer Arithmetic IP Cores User Guide Document Archives
16. Document Revision History for Intel FPGA Integer Arithmetic IP Cores User Guide

8.5. Signals

The following tables list the input and output signals of the Multiply Adder Intel® FPGA IP or ALTERA_MULT_ADD IP core.

Table 28.   Multiply Adder Intel® FPGA IP or ALTERA_MULT_ADD Input Signals
Signal Required Description
dataa_0[]/dataa_1[]/dataa_2[]/dataa_3[] Yes Data input to the multiplier. Input port [NUMBER_OF_MULTIPLIERS * WIDTH_A - 1 … 0] wide

The simulation model for this IP supports undetermined input value (X) to these signals. When you provide X value to these signals,the X value is propagated on the output signals.

datab_0[]/datab_1[]/datab_2[]/datab_3[] Yes Data input to the multiplier. Input signal [NUMBER_OF_MULTIPLIERS * WIDTH_B - 1 … 0] wide

The simulation model for this IP supports undetermined input value (X) to these signals. When you provide X value to these signals, the X value is propagated on the output signals.

datac_0[] /datac_1[]/datac_2[]/datac_3[] No Data input to the multiplier. Input signal [NUMBER_OF_MULTIPLIERS * WIDTH_C - 1, … 0] wide

Select INPUT for Select preadder mode parameter to enable these signals.

The simulation model for this IP supports undetermined input value (X) to these signals. When you provide X value to these signals, the X value is propagated on the output signals.

clock[1:0] No Clock input port to the corresponding register. This signal can be used by any register in the IP core.

The simulation model for this IP supports undetermined input value (X) to these signals. When you provide X value to these signals, the X value is propagated on the output signals.

aclr[1:0] No Asynchronous clear input to the corresponding register.

The simulation model for this IP supports undetermined input value (X) to these signals. When you provide X value to these signals, the X value is propagated on the output signals.

sclr[1:0] No Synchronous clear input to the corresponding register.

The simulation model for this IP supports undetermined input value X to these signals. When you provide X value to these signals, the X value is propagated on the output signals

ena[1:0] No Enable signal input to the corresponding register.

The simulation model for this IP supports undetermined input value (X) to these signals. When you provide X value to these signals, the X value is propagated on the output signals.

signa No Specifies the numerical representation of the multiplier input A. If the signa signal is high, the multiplier treats the multiplier input A signal as a signed number. If the signa signal is low, the multiplier treats the multiplier input A signal as an unsigned number.

Select VARIABLE for What is the representation format for Multipliers A inputs parameter to enable this signal.

The simulation model for this IP supports undetermined input value (X) to this signal. When you provide X value to this input, the X value is propagated on the output signals.

signb No Specifies the numerical representation of the multiplier input B signal. If the signb signal is high, the multiplier treats the multiplier input B signal as a signed two's complement number. If the signb signal is low, the multiplier treats the multiplier input B signal as an unsigned number.

The simulation model for this IP supports undetermined input value (X) to this signal. When you provide X value to this input, the X value is propagated on the output signals.

scanina[] No Input for scan chain A. Input signal [WIDTH_A - 1, ... 0] wide. When the INPUT_SOURCE_A parameter has a value of SCANA, the scanina[] signal is required.
accum_sload No Dynamically specifies whether the accumulator value is constant. If the accum_sload signal is low, then the multiplier output is loaded into the accumulator. Do not use accum_sload and sload_accum simultaneously.

The simulation model for this IP supports undetermined input value (X) to this signal. When you provide X value to this input, the X value is propagated on the output signals.

sload_accum No Dynamically specifies whether the accumulator value is constant. If the sload_accum signal is high, then the multiplier output is loaded into the accumulator. Do not use accum_sload and sload_accum simultaneously.

The simulation model for this IP supports undetermined input value (X) to this signal. When you provide X value to this input, the X value is propagated on the output signals.

chainin[] No Adder result input bus from the preceding stage. Input signal [WIDTH_CHAININ - 1, … 0] wide.
addnsub1 No Perform addition or subtraction to the outputs from the first pair of multipliers. Input 1 to addnsub1 signal to add the outputs from the first pair of multipliers. Input 0 to addnsub1 signal to subtract the outputs from the first pair of multipliers.

The simulation model for this IP supports undetermined input value (X) to this signal. When you provide X value to this input, the X value is propagated on the output signals.

addnsub3 No Perform addition or subtraction to the outputs from the first pair of multipliers. Input 1 to addnsub3 signal to add the outputs from the second pair of multipliers. Input 0 to addnsub3 signal to subtract the outputs from the first pair of multipliers.

The simulation model for this IP supports undetermined input value (X) to this signal. When you provide X value to this input, the X value is propagated on the output signals.

coefsel0[] No Coefficient input signal[0:3] to the first multiplier.

The simulation model for this IP supports undetermined input value (X) to this signal. When you provide X value to this input, the X value is propagated on the output signals.

coefsel1[] No Coefficient input signal[0:3]to the second multiplier.

The simulation model for this IP supports undetermined input value (X) to this signal. When you provide X value to this input, the X value is propagated on the output signals.

coefsel2[] No Coefficient input signal[0:3]to the third multiplier.

The simulation model for this IP supports undetermined input value (X) to this signal. When you provide X value to this input, the X value is propagated on the output signals.

coefsel3[] No Coefficient input signal [0:3] to the fourth multiplier.

The simulation model for this IP supports undetermined input value (X) to this signal. When you provide X value to this input, the X value is propagated on the output signals.

Table 29.   Multiply Adder Intel® FPGA IP Output Signals
Signal Required Description
result [] Yes Multiplier output signal. Output signal [WIDTH_RESULT - 1 … 0] wide

The simulation model for this IP supports undetermined output value (X). When you provide X value as the input, the X value is propagated on this signal.

scanouta [] No Output of scan chain A. Output signal [WIDTH_A - 1..0] wide.

Select more than 2 for numbers of multipliers and choose Scan chain input

for What is the input A of the multiplier connected to parameter to enable this signal.
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