Stratix® 10 SX SoC Development Kit User Guide

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ID 683303
Date 6/06/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Development Kit Components 5. Board Test System A. Additional Information B. Document Revision History for the Stratix® 10 10 SX SoC Development Kit User Guide
1. Overview x
1.1. General Development Kit Description 1.2. Recommended Operating Conditions 1.3. Handling the Development Kit
2. Getting Started x
2.1. Installing Quartus® Prime Software 2.2. Installing the Intel® FPGA Download Cable 2.3. Installing the Intel SoC Embedded Development Suite (EDS) 2.4. Installing the Stratix® 10 SX SoC Development Kit Package
3. Development Kit Setup x
3.1. Inspect the Development Kit 3.2. Default Setup of the Development Kit 3.3. MAX® 10 System Controller Updates
4. Development Kit Components x
4.1. Development Kit Feature Summary 4.2. Board Components 4.3. Stratix® 10 SoC Device Overview 4.4. MAX® 10 System Controller Overview 4.5. FPGA Configuration 4.6. General User Input/Output 4.7. Connectors and Interfaces 4.8. Daughter Cards 4.9. System Memory 4.10. System Power
4.7. Connectors and Interfaces x
4.7.1. PCIe* Slot 4.7.2. ZQSFP+ 4.7.3. SFP+ 4.7.4. HDMI 4.7.5. SDI Port 4.7.6. MXP 4.7.7. Intel® FPGA Download Cable Direct Port (Debug Port) 4.7.8. FMC+ A/B Slot 4.7.9. FMC+ A/B LVDS Interfaces (LPC Pins) 4.7.10. LMK05028 Jitter Attenuator 4.7.11. FPGA-IOMAX10 Interface
4.8. Daughter Cards x
4.8.1. HPS IO-48 OOBE Daughter Card 4.8.2. HPS IO-48 NAND Flash Daughter Card 4.8.3. HPS Boot Flash Card
4.8.3. HPS Boot Flash Card x
4.8.3.1. Boot QSPI Flash Daughter Card 4.8.3.2. Boot MicroSD Daughter Card 4.8.3.3. Boot eMMC Daughter Card
4.9. System Memory x
4.9.1. FPGA Memory (DDR4 SO-DIMM) 4.9.2. HPS Memory (External 4 GB HILO x72 DDR4) 4.9.3. HPS I2C Interface
4.10. System Power x
4.10.1. Power Supply Options 4.10.2. Power Sequence 4.10.3. Power Distribution Network
5. Board Test System x
5.1. Preparing the Board 5.2. Running the BTS 5.3. Using the BTS
5.3. Using the BTS x
5.3.1. The Configure Menu 5.3.2. The GPIO Tab 5.3.3. The QSFP/SFP Tab 5.3.4. The PCIE Tab 5.3.5. The MXP Tab 5.3.6. The FMCA Tab 5.3.7. The FMCB Tab 5.3.8. The DDR4 Tab 5.3.9. Power Monitor 5.3.10. The Clock Control
A. Additional Information x
A.1. Modify the Stratix® 10 SX SoC Development Kit to use a battery for the BBRAM A.2. Modify the Stratix® 10 SX SoC Development Kit HPS DDR4 memory width and ECC configuration using the Golden Hardware Reference Design project A.3. Safety and Regulatory Information A.4. Compliance Information
A.3. Safety and Regulatory Information x
A.3.1. Safety Warnings A.3.2. Safety Cautions
A.4. Compliance Information x
A.4.1. Compliance and Conformity Statements
1. Overview
2. Getting Started
3. Development Kit Setup
4. Development Kit Components
5. Board Test System
A. Additional Information
B. Document Revision History for the Stratix® 10 10 SX SoC Development Kit User Guide

4.7.2. ZQSFP+

The ZQSFP+ 0/1 ports meet SFF8665 and QSFP28 industrial standards. The connector part number is Molex 170432-001. The cage part number is TE 2227103-2. The PCB trace insertion loss is less than -5 dB and return loss is less than -10 dB. The ZQSFP+ signals (Modesl, RESETL, MOdPrsl, LPmode, int) are mapped to the dedicated I/O in System MAX® 10. The BC25, BC26 pins in 2F bank are I2C interface. The user needs this interface to access ZQSFP.

Table 14.  ZQSFP+ 0/1 Ports FPGA Pin Map
Pin Name Schematic Signal Name Direction Description
PIN_P9 CLEARNER_XVR_644.53125MHZ_P Input REFCLK_GXBR4N_CHTP
PIN_P10 CLEARNER_XVR_644.53125MHZ_N Input REFCLK_GXBR4N_CHTN
PIN_C4 ZQSFP0_TXN3 Output GXBR4N_TX_CH3N
PIN_C3 ZQSFP0_TXP3 Output GXBR4N_TX_CH3P
PIN_A8 ZQSFP0_RXN3 Input GXBR4N_RX_CH3N
PIN_A7 ZQSFP0_RXP3 Input GXBR4N_RX_CH3P
PIN_E4 ZQSFP0_TXN2 Output GXBR4N_TX_CH2N
PIN_E3 ZQSFP0_TXP2 Output GXBR4N_TX_CH2P
PIN_C8 ZQSFP0_RXN2 Input GXBR4N_RX_CH2N
PIN_C7 ZQSFP0_RXP2 Input GXBR4N_RX_CH2P
PIN_G4 ZQSFP0_TXN1 Output GXBR4N_TX_CH1N
PIN_G3 ZQSFP0_TXP1 Output GXBR4N_TX_CH1P
PIN_D6 ZQSFP0_RXN1 Input GXBR4N_RX_CH1N
PIN_D5 ZQSFP0_RXP1 Input GXBR4N_RX_CH1P
PIN_F2 ZQSFP0_TXN0 Output GXBR4N_TX_CH0N
PIN_F1 ZQSFP0_TXP0 Output GXBR4N_TX_CH0P
PIN_G8 ZQSFP0_RXN0 Input GXBR4N_RX_CH0N
PIN_G7 ZQSFP0_RXP0 Input GXBR4N_RX_CH0P
PIN_T9 REFCLK0_P Input REFCLK_GXBR4N_CHBP
PIN_T10 REFCLK0_N Input REFCLK_GXBR4N_CHBN
PIN_AF2 ZQSFP1_TXN3 Output GXBR4F_TX_CH3N
PIN_AF1 ZQSFP1_TXP3 Output GXBR4F_TX_CH3P
PIN_AG8 ZQSFP1_RXN3 Input GXBR4F_RX_CH3N
PIN_AG7 ZQSFP1_RXP3 Input GXBR4F_RX_CH3P
PIN_AJ4 ZQSFP1_TXN2 Output GXBR4F_TX_CH2N
PIN_AJ3 ZQSFP1_TXP2 Output GXBR4F_TX_CH2P
PIN_AF6 ZQSFP1_RXN2 Input GXBR4F_RX_CH2N
PIN_AF5 ZQSFP1_RXP2 Input GXBR4F_RX_CH2P
PIN_AL4 ZQSFP1_TXN1 Output GXBR4F_TX_CH1N
PIN_AL3 ZQSFP1_TXP1 Output GXBR4F_TX_CH1P
PIN_AH6 ZQSFP1_RXN1 Input GXBR4F_RX_CH1N
PIN_AH5 ZQSFP1_RXP1 Input GXBR4F_RX_CH1P
PIN_AK2 ZQSFP1_TXN0 Output GXBR4F_TX_CH0N
PIN_AK1 ZQSFP1_TXP0 Output GXBR4F_TX_CH0P
PIN_AL8 ZQSFP1_RXN0 Input GXBR4F_RX_CH0N
PIN_AL7 ZQSFP1_RXP0 Input GXBR4F_RX_CH0P
PIN_AM12 REFCLK_QSFP1_P Input REFCLK_GXBR4F_CHBP
PIN_AM13 REFCLK_QSFP1_N Input REFCLK_GXBR4F_CHBN
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