Stratix® 10 SX SoC Development Kit User Guide

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ID 683303
Date 6/06/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Development Kit Components 5. Board Test System A. Additional Information B. Document Revision History for the Stratix® 10 10 SX SoC Development Kit User Guide
1. Overview x
1.1. General Development Kit Description 1.2. Recommended Operating Conditions 1.3. Handling the Development Kit
2. Getting Started x
2.1. Installing Quartus® Prime Software 2.2. Installing the Intel® FPGA Download Cable 2.3. Installing the Intel SoC Embedded Development Suite (EDS) 2.4. Installing the Stratix® 10 SX SoC Development Kit Package
3. Development Kit Setup x
3.1. Inspect the Development Kit 3.2. Default Setup of the Development Kit 3.3. MAX® 10 System Controller Updates
4. Development Kit Components x
4.1. Development Kit Feature Summary 4.2. Board Components 4.3. Stratix® 10 SoC Device Overview 4.4. MAX® 10 System Controller Overview 4.5. FPGA Configuration 4.6. General User Input/Output 4.7. Connectors and Interfaces 4.8. Daughter Cards 4.9. System Memory 4.10. System Power
4.7. Connectors and Interfaces x
4.7.1. PCIe* Slot 4.7.2. ZQSFP+ 4.7.3. SFP+ 4.7.4. HDMI 4.7.5. SDI Port 4.7.6. MXP 4.7.7. Intel® FPGA Download Cable Direct Port (Debug Port) 4.7.8. FMC+ A/B Slot 4.7.9. FMC+ A/B LVDS Interfaces (LPC Pins) 4.7.10. LMK05028 Jitter Attenuator 4.7.11. FPGA-IOMAX10 Interface
4.8. Daughter Cards x
4.8.1. HPS IO-48 OOBE Daughter Card 4.8.2. HPS IO-48 NAND Flash Daughter Card 4.8.3. HPS Boot Flash Card
4.8.3. HPS Boot Flash Card x
4.8.3.1. Boot QSPI Flash Daughter Card 4.8.3.2. Boot MicroSD Daughter Card 4.8.3.3. Boot eMMC Daughter Card
4.9. System Memory x
4.9.1. FPGA Memory (DDR4 SO-DIMM) 4.9.2. HPS Memory (External 4 GB HILO x72 DDR4) 4.9.3. HPS I2C Interface
4.10. System Power x
4.10.1. Power Supply Options 4.10.2. Power Sequence 4.10.3. Power Distribution Network
5. Board Test System x
5.1. Preparing the Board 5.2. Running the BTS 5.3. Using the BTS
5.3. Using the BTS x
5.3.1. The Configure Menu 5.3.2. The GPIO Tab 5.3.3. The QSFP/SFP Tab 5.3.4. The PCIE Tab 5.3.5. The MXP Tab 5.3.6. The FMCA Tab 5.3.7. The FMCB Tab 5.3.8. The DDR4 Tab 5.3.9. Power Monitor 5.3.10. The Clock Control
A. Additional Information x
A.1. Modify the Stratix® 10 SX SoC Development Kit to use a battery for the BBRAM A.2. Modify the Stratix® 10 SX SoC Development Kit HPS DDR4 memory width and ECC configuration using the Golden Hardware Reference Design project A.3. Safety and Regulatory Information A.4. Compliance Information
A.3. Safety and Regulatory Information x
A.3.1. Safety Warnings A.3.2. Safety Cautions
A.4. Compliance Information x
A.4.1. Compliance and Conformity Statements
1. Overview
2. Getting Started
3. Development Kit Setup
4. Development Kit Components
5. Board Test System
A. Additional Information
B. Document Revision History for the Stratix® 10 10 SX SoC Development Kit User Guide

4.3. Stratix® 10 SoC Device Overview

Altera's 14-nm Stratix® 10 SX SoCs deliver 2x core performance and up to 70% lower power over previous generation high-performance SoCs. Featuring several groundbreaking innovations, including the all new Hyperflex® core architecture, this device family enables you to meet the demand for ever-increasing bandwidth and processing performance in you most advanced applications, while meeting your power budget.

Featuring several groundbreaking innovations, including the all new HyperFlex™ core architecture, this device family enables you to meet the demand for ever-increasing bandwidth and processing performance in your most advanced applications, while meeting your power budget.

With an embedded hard processor system (HPS) based on a quad-core 64-bit Arm* Cortex* -A53, the Stratix® 10 SoC devices deliver power efficient, application-class processing and allow designers to extend hardware virtualization into the FPGA fabric. The Stratix® 10 SoC devices demonstrate Altera's commitment to high-performance SoCs and extend Altera's leadership in programmable devices featuring an Arm* -based processor system.

Important innovations in Stratix® 10 FPGAs and SoCs include:

  • All new HyperFlex core architecture delivering 2X the core performance compared to previous generation high-performance FPGAs
  • Industry leading Intel 14-nm Tri-Gate (FinFET) technology
  • Heterogeneous 3D System-in-Package (SiP) technology
  • Monolithic core fabric with up to 5.5 million logic elements (LEs)
  • Up to 96 full duplex transceiver channels on heterogeneous 3D SiP transceiver tiles
  • Transceiver data rates up to 28.3 Gbps chip-to-chip/module and backplane performance
  • Embedded eSRAM (45 Mbit) and M20K (20 kbit) internal SRAM memory blocks
  • Fractional synthesis and ultra-low jitter LC tank based transmit phase locked loops (PLLs)
  • Hard PCI Express® Gen3 x16 intellectual property (IP) blocks
  • Hard 10GBASE-KR/40GBASE-KR4 Forward Error Correction (FEC) in every transceiver channel
  • Hard memory controllers and PHY supporting DDR4 rates up to 2666 Mbps per pin
  • Hard fixed-point and IEEE 754 compliant hard floating-point variable precision digital signal processing (DSP) blocks with up to 10 TFLOPS compute performance with a power efficiency of 80 GFLOPS per Watt
  • Quad-core 64-bit Arm* Cortex-A53 embedded processor running up to 1.5 GHz in SoC family variants
  • Programmable clock tree synthesis for flexible, low power, low skew clock trees
  • Dedicated secure device manager (SDM) for:
    • Enhanced device configuration and security
    • AES-256, SHA-256/384 and ECDSA-256/384 encrypt/decrypt accelerators and authentication
    • Multi-factor authentication
    • Physically Unclonable Function (PUF) service and software programmable device configuration capability
  • Comprehensive set of advanced power saving features delivering up to 70% lower power compared to previous generation high-performance FPGAs
  • Non-destructive register state readback and writeback, to support ASIC prototyping and other applications

With these capabilities, Stratix 10 FPGAs and SoCs are ideally suited for the most demanding applications in diverse markets such as:

  • Compute and Storage—for custom servers, cloud computing and data center acceleration
  • Networking—for Terabit, 400G and multi-100G bridging, aggregation, packet processing and traffic management
  • Optical Transport Networks—for OTU4, 2xOTU4, 4xOTU4
  • Broadcast—for high-end studio distribution, head-end encoding/decoding, edge quadrature amplitude modulation (QAM)
  • Military—for radar, electronic warfare, and secure communications
  • Medical—for diagnostic scanners and diagnostic imaging
  • Test and Measurement—for protocol and application testers
  • Wireless—for next-generation 5G networks
  • ASIC Prototyping—for designs that require the largest monolithic FPGA fabric with the highest I/O count

Stratix® 10 SX SoC devices have a feature set that is identical to the Stratix® 10 FPGA devices, with the addition of an embedded quad-core 64-bit Arm* Cortex* A53 Hard Processor System.

Common to all Stratix® 10 family variants is a high-performance fabric based on the new HyperFlex core architecture that includes additional Hyper-Registers throughout the interconnect routing and at the inputs of all functional blocks. The core fabric also contains an enhanced logic array utilizing Altera’s adaptive logic module (ALM) and a rich set of high performance building blocks including:

To clock these building blocks, Stratix® 10 devices use programmable clock tree synthesis, which uses dedicated clock tree routing to synthesize only those branches of the clock trees required for the application. All devices support in-system, fine-grained partial reconfiguration of the logic array, allowing logic to be added and subtracted from the system while it is operating.

All family variants also contain high speed serial transceivers, containing both the physical medium attachment (PMA) and the physical coding sublayer (PCS), which can be used to implement a variety of industry standard and proprietary protocols. In addition to the hard PCS, Stratix® 10 devices contain multiple instantiations of PCI Express hard IP that supports Gen1/Gen2/Gen3 rates in x1/x2/x4/x8/x16 lane configurations, and hard 10GBASE-KR/40GBASE-KR4 FEC for every transceiver. The hard PCS, FEC, and PCI Express IP free up valuable core logic resources, save power, and increase your productivity.

Table 6.  Stratix 10 FPGA and SoC Common Device Features

Feature

Description

Technology

  • 14-nm Intel Tri-Gate (FinFET) process technology
  • SmartVoltage ID (VID) controlled standard VCC option
  • 0.8 V and 0.85 V optional VCC core voltage

Low power serial transceivers

  • Up to 96 total transceivers available
  • Continuous operating range of 1 Gbps to 28.3 Gbps for Stratix® 10 GX/SX devices
  • Backplane support up to 28.3 Gbps for Stratix® 10 GX/SX devices
  • Extended range down to 125 Mbps with oversampling
  • ATX transmit PLLs with user-configurable fractional synthesis capability
  • XFP, SFP+, QSFP/QSFP28, CFP/CFP2/CFP4 optical module support
  • Adaptive linear and decision feedback equalization
  • Transmit pre-emphasis and de-emphasis
  • Dynamic partial reconfiguration of individual transceiver channels
  • On-chip instrumentation (EyeQ non-intrusive data eye monitoring)

General purpose I/Os

  • Up to 1640 total GPIO available
  • 1.6 Gbps LVDS—every pair can be configured as an input or output
  • 1333 MHz/2666 Mbps DDR4 external memory interface
  • 1067 MHz/2133 Mbps DDR3 external memory interface
  • 1.2 V to 3.0 V single-ended LVCMOS/LVTTL interfacing
  • On-chip termination (OCT)

Embedded hard IP

  • PCIe* Gen1/Gen2/Gen3 complete protocol stack, x1/x2/x4/x8/x16 end point and root port
  • DDR4/DDR3/LPDDR3 hard memory controller (RLDRAM3/QDR II+/QDR IV using soft memory controller)
  • Multiple hard IP instantiations in each device
  • Single Root I/O Virtualization (SR-IOV)

Transceiver hard IP

  • 10GBASE-KR/40GBASE-KR4 Forward Error Correction (FEC)
  • 10G Ethernet PCS
  • PCI Express* PIPE interface
  • Interlaken PCS
  • Gigabit Ethernet PCS
  • Deterministic latency support for Common Public Radio Interface (CPRI) PCS
  • Fast lock-time support for Gigabit Passive Optical Networking (GPON) PCS
  • 8B/10B, 64B/66B, 64B/67B encoders and decoders
  • Custom mode support for proprietary protocols

Power management

  • SmartVoltage ID controlled standard VCC option
  • Low static power device options
  • Quartus® Prime Pro Edition integrated power analysis

High performance monolithic core fabric

  • HyperFlex core architecture with Hyper-Registers throughout the interconnect routing and at the inputs of all functional blocks
  • Monolithic fabric minimizes compile times and increases logic utilization
  • Enhanced adaptive logic module (ALM)
  • Improved multi-track routing architecture reduces congestion and improves compile times
  • Hierarchical core clocking architecture with programmable clock tree synthesis
  • Fine-grained partial reconfiguration

Internal memory blocks

  • eSRAM - 45-Mbit with hard ECC support
  • M20K—20-Kbit with hard ECC support
  • MLAB—640-bit distributed LUTRAM

Variable precision DSP blocks

  • IEEE 754-compliant hard single-precision floating point capability
  • Supports signal processing with precision ranging from 18x19 up to 54x54
  • Native 27x27 and 18x19 multiply modes
  • 64-bit accumulator and cascade for systolic FIRs
  • Internal coefficient memory banks
  • Pre-adder/subtractor improves efficiency
  • Additional pipeline register increases performance and reduces power

Phase locked loops (PLL)

  • Fractional synthesis PLLs (fPLL) support both fractional and integer modes
  • Fractional mode with third-order delta-sigma modulation
  • Precision frequency synthesis
  • Integer PLLs adjacent to general purpose I/Os, support external memory, and LVDS interfaces, clock delay compensation, zero delay buffering

Core clock networks

  • 1 GHz fabric clocking
  • 667 MHz external memory interface clocking, supports 2666 Mbps DDR4 interface
  • 800 MHz LVDS interface clocking, supports 1600 Mbps LVDS interface
  • Programmable clock tree synthesis, backwards compatible with global, regional and peripheral clock networks
  • Clocks only synthesized where needed, to minimize dynamic power

Configuration

  • Dedicated Secure Device Manager
  • Software programmable device configuration
  • Serial and parallel flash interface
  • Configuration via protocol (CvP) using PCI Express Gen1/Gen2/Gen3
  • Fine-grained partial reconfiguration of core fabric
  • Dynamic reconfiguration of transceivers and PLLs
  • Comprehensive set of security features including AES-256, SHA-256/384, and ECDSA-256/384 accelerators, and multi-factor authentication
  • Physically Unclonable Function (PUF) service

Packaging

  • Intel Embedded Multi-die Interconnect Bridge (EMIB) packaging technology
  • Multiple devices with identical package footprints allows seamless migration across different device densities
  • 1.0 mm ball-pitch FBGA packaging
  • Lead and lead-free package options

Software and tools

  • Quartus® Prime Pro Edition design suite with new Spectra-Q engine and Hyper-Aware design flow
  • Fast Forward compiler to allow HyperFlex architecture performance exploration
  • Transceiver toolkit
  • Qsys system integration tool
  • DSP Builder advanced blockset
  • OpenCL™ support
  • SoC Embedded Design Suite (EDS)
Table 7.   Stratix® 10 SoC Specific Device Features
SoC Subsystem Feature Description
Hard Processor System Multi-processor unit (MPU) core
  • Quad-core Arm* Cortex-A53 MPCore processor with Arm* CoreSight debug and trace technology
  • Scalar floating-point unit supporting single and double precision
  • Arm* NEON media processing engine for each processor
System Controllers
  • System Memory Management Unit (SMMU)
  • Cache Coherency Unit (CCU)
Layer 1 Cache
  • 32 KB L1 instruction cache with parity
  • 32 KB L1 data cache with ECC
Layer 2 Cache
  • 1 MB Shared L2 Cache with ECC
On-Chip Memory
  • 256 KB On-Chip RAM
Direct memory access (DMA) controller
  • 8-Channel DMA
Ethernet media access controller (EMAC)
  • Three 10/100/1000 EMAC with integrated DMA
USB On-The-Go controller (OTG)
  • 2 USB OTG with integrated DMA
UART controller
  • 2 UART 16550 compatible
Serial Peripheral Interface (SPI) controller
  • 4 SPI
I2C controller
  • 5 I2C controllers
SD/SDIO/MMC controller
  • 1 eMMC version 4.5 with DMA and CE-ATA support
  • SD, including eSD, version 3.0
  • SDIO, including eSDIO, version 3.0
  • CE-ATA - version 1.1
NAND flash controller
  • 1 ONFI 1.0, 8- and 16-bit support
General-purpose I/O (GPIO)
  • Maximum of 48 software programmable GPIO
Timers
  • 4 general-purpose timers
  • 4 watchdog timers
Secure Device Manager Security
  • Secure boot
  • Advanced Encryption Standard (AES) and authentication (SHA/ECDSA)
External Memory Interface External Memory Interface
  • Hard Memory Controller with DDR4 and DDR3, and LPDDR3

For further information, refer to the Stratix® 10 GX/SX Device Overview available on the Intel website.

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