Stratix® 10 SX SoC Development Kit User Guide

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ID 683303
Date 6/06/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Development Kit Components 5. Board Test System A. Additional Information B. Document Revision History for the Stratix® 10 10 SX SoC Development Kit User Guide
1. Overview x
1.1. General Development Kit Description 1.2. Recommended Operating Conditions 1.3. Handling the Development Kit
2. Getting Started x
2.1. Installing Quartus® Prime Software 2.2. Installing the Intel® FPGA Download Cable 2.3. Installing the Intel SoC Embedded Development Suite (EDS) 2.4. Installing the Stratix® 10 SX SoC Development Kit Package
3. Development Kit Setup x
3.1. Inspect the Development Kit 3.2. Default Setup of the Development Kit 3.3. MAX® 10 System Controller Updates
4. Development Kit Components x
4.1. Development Kit Feature Summary 4.2. Board Components 4.3. Stratix® 10 SoC Device Overview 4.4. MAX® 10 System Controller Overview 4.5. FPGA Configuration 4.6. General User Input/Output 4.7. Connectors and Interfaces 4.8. Daughter Cards 4.9. System Memory 4.10. System Power
4.7. Connectors and Interfaces x
4.7.1. PCIe* Slot 4.7.2. ZQSFP+ 4.7.3. SFP+ 4.7.4. HDMI 4.7.5. SDI Port 4.7.6. MXP 4.7.7. Intel® FPGA Download Cable Direct Port (Debug Port) 4.7.8. FMC+ A/B Slot 4.7.9. FMC+ A/B LVDS Interfaces (LPC Pins) 4.7.10. LMK05028 Jitter Attenuator 4.7.11. FPGA-IOMAX10 Interface
4.8. Daughter Cards x
4.8.1. HPS IO-48 OOBE Daughter Card 4.8.2. HPS IO-48 NAND Flash Daughter Card 4.8.3. HPS Boot Flash Card
4.8.3. HPS Boot Flash Card x
4.8.3.1. Boot QSPI Flash Daughter Card 4.8.3.2. Boot MicroSD Daughter Card 4.8.3.3. Boot eMMC Daughter Card
4.9. System Memory x
4.9.1. FPGA Memory (DDR4 SO-DIMM) 4.9.2. HPS Memory (External 4 GB HILO x72 DDR4) 4.9.3. HPS I2C Interface
4.10. System Power x
4.10.1. Power Supply Options 4.10.2. Power Sequence 4.10.3. Power Distribution Network
5. Board Test System x
5.1. Preparing the Board 5.2. Running the BTS 5.3. Using the BTS
5.3. Using the BTS x
5.3.1. The Configure Menu 5.3.2. The GPIO Tab 5.3.3. The QSFP/SFP Tab 5.3.4. The PCIE Tab 5.3.5. The MXP Tab 5.3.6. The FMCA Tab 5.3.7. The FMCB Tab 5.3.8. The DDR4 Tab 5.3.9. Power Monitor 5.3.10. The Clock Control
A. Additional Information x
A.1. Modify the Stratix® 10 SX SoC Development Kit to use a battery for the BBRAM A.2. Modify the Stratix® 10 SX SoC Development Kit HPS DDR4 memory width and ECC configuration using the Golden Hardware Reference Design project A.3. Safety and Regulatory Information A.4. Compliance Information
A.3. Safety and Regulatory Information x
A.3.1. Safety Warnings A.3.2. Safety Cautions
A.4. Compliance Information x
A.4.1. Compliance and Conformity Statements
1. Overview
2. Getting Started
3. Development Kit Setup
4. Development Kit Components
5. Board Test System
A. Additional Information
B. Document Revision History for the Stratix® 10 10 SX SoC Development Kit User Guide

4.1. Development Kit Feature Summary

Table 4.   Stratix® 10 SoC Development Kit Feature Summary
Feature Description
Programmable Logic
  • Stratix® 10 SoC FPGA
  • 10M04SCU169C8G MAX® 10 CPLD as the Intel® FPGA Download Cable and JTAG switch device
  • 10M16SAU169C8G MAX® 10 CPLD as the Power manager and sequencer device
  • 10M50DAF484I7G MAX® 10 CPLD as the IO level translator, IO MUX and Passive AVST-16 FPGA controller device
HPS memory 1066 MHz 4 GB 72-bit HILO memory card
HPS Boot Flash (Flash Card)
  • Boot Codes for QSPI, SD Micro
  • QSPI Flash: 256 MB (MT25QU02GCBB8E12-0SIT)
  • SD Micro Flash Card: 16 GB (Kingston)
HPS IO48 OOBE Daughter Card
  • One HPS IO48 60-pin Samtec Connector
  • One RGMII 10/100/1000 Mbps Ethernet port: Standard RJ-45
  • One UART port: Standard USB Mini-B Receptacle
  • One Micro SD Card Connector: Standard Micro SD Card Socket
  • One USB 2.0 port: Standard USB Micro-AB Receptacle
  • One Mictor 38-pin connector (JTAG only without Trace signals)
    • Two JTAG targets selected by the resistors MUX: FPGA JTAG chain (optional) and HPS JTAG Port (default)
  • I2C: HPS I2C port
  • GPIO
    • 2 Push buttons
    • 3 LEDs
    • 1 Ethernet Interrupt from Ethernet PHY
    • 1 USB over-current indicator
  • HPS Clock: 25 MHz oscillator
HPS IO48 NAND Flash Daughter Card
  • One HPS IO48 60-pin Samtec connector
  • One RGMII 10/100/1000 Mbps Ethernet port: Standard RJ-45
  • One UART port: Standard USB Mini-B Receptacle
  • NAND Flash (x16): 8 Gb
  • eMMC (x8): 8 GB 5.0 compliant eMMC
  • I2C: HPS I2C port
  • GPIO
    • 2 Push Buttons
    • 3 LEDs
    • 1 Ethernet Interrupt from Ethernet PHY
  • HPS Clock: 25 MHz oscillator
FPGA memory 1200 MHz 16 GB DDR4 SO-DIMM MTA18ASF2G72HZ – 2G6
FPGA File Flash (Flash Card)
  • NAND Flash (x8): 1 GB
  • QSPI Flash: 256 MB
  • SD Micro Flash Card: 16 GB (Kingston)
Two V57.4 High Pin Count FMC+ Slots
  • 28 Gbps signals: Insertion loss less than 5 dB, return loss less than 10 dB
  • FMC+ PCIe* Gen3 x16 cable (not included)
  • FMC to PCIe* Gen3 x8 cable (not included)
  • 16/32 bit trace
Note: FMC to PCIe cables are sold separately by Samtec. Please contact them directly regarding P/N HDR-201768-01-PCIEC
FPGA PCIe* Gen 1/2/3 x16 RC Slot
  • 75 W Power
  • Meets PCIe* specifications
FPGA Communication Ports
  • Two 28 Gbps ZQSFP+ Ports: 100/50 Gbps IP, Insertion loss less than 5 dB, return loss less than 10 dB
  • One 10 Gbps SFP+ Port: 10 Gbps Ethernet IP
  • SMA Test Port: Up to four 28 Gbps channels, insertion loss less than 5 dB, return loss less than 10 dB, one external reference clock
  • One DB-9 RS-232 Port (MAX3221)
FPGA Debug Ports Intel® FPGA Download Cable Direct Port & JTAG
FPGA Reference Clocks
  • Clock Cleaner
    • 122.88 MHz (Network)
    • 644.5312 MHz (Network)
    • 297 MHz (SDI)
    • 245 MHz (SDI)
  • Clock Generators
    • LMH1983 (27 MHz, 148.5 MHz)
    • Si5388 (133.33 MHz)
    • PCIe (100 MHz)
    • Si5338 (148 MHz, 100 MHz, 27 MHz, 100 MHz)
    • Si5341 (155.52 MHz, 644.53125 MHz, 135 MHz, 156.25 MHz, 625 MHz, 100 MHz, 125 MHz, 125 MHz)
I2C Devices
  • 4 KB SEEPROM
  • Real Time Clock
  • Silicon Labs™ Clock Generators
  • FMC+ Slots
  • PCIe Slots
  • SFP+
  • ZQSFP
  • Clock Cleaner
  • Power Supplies
MAX® 10 Controller I/O CPLD Features
  • System Reset Controller
  • FPGA PS AVST Configuration Controller
  • I2C Master Controller
  • UART Level Shifter
  • FPGA I/O MUX
  • SDI/HDMI/QSFP/SFP+ I/O level shift
MAX® 10 Power CPLD Sequencer FPGA, PCIe, FMC+ slots power sequencer, Reset.
MAX® 10 CPLD Features
  • Intel® FPGA Download Cable II
  • JTAG Switch
    • Input JTAG Sources ( Intel® FPGA Download Cable II, 10-pin Program Header, FMCA+, FMCB+, Mictor JTAG)
    • Output JTAG Sources ( MAX® 10 A JTAG, MAX10B JTAG, Stratix® 10 JTAG, FMCA+, FMCB+, PCIe)
    • JTAG Program
    • User I/O
User I/O
  • 4 Push Buttons
  • 4-bit Dipswitch
  • 4 User LEDs
  • 2-pin I/O Header
  • System MAX® 10 LEDs and 4-bit switch
Power
  • Volgen KTPS200-12160, 12V, 24A
  • ATX-Power
Mechanical
  • 8.5" x 14.5" Rectangular Form Factor
  • Liquid cool thermal heat sink (300W @ 35C)
System Monitor Power, Voltage, Current
Level Two Title