Stratix® 10 SX SoC Development Kit User Guide

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ID 683303
Date 6/06/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Development Kit Components 5. Board Test System A. Additional Information B. Document Revision History for the Stratix® 10 10 SX SoC Development Kit User Guide
1. Overview x
1.1. General Development Kit Description 1.2. Recommended Operating Conditions 1.3. Handling the Development Kit
2. Getting Started x
2.1. Installing Quartus® Prime Software 2.2. Installing the Intel® FPGA Download Cable 2.3. Installing the Intel SoC Embedded Development Suite (EDS) 2.4. Installing the Stratix® 10 SX SoC Development Kit Package
3. Development Kit Setup x
3.1. Inspect the Development Kit 3.2. Default Setup of the Development Kit 3.3. MAX® 10 System Controller Updates
4. Development Kit Components x
4.1. Development Kit Feature Summary 4.2. Board Components 4.3. Stratix® 10 SoC Device Overview 4.4. MAX® 10 System Controller Overview 4.5. FPGA Configuration 4.6. General User Input/Output 4.7. Connectors and Interfaces 4.8. Daughter Cards 4.9. System Memory 4.10. System Power
4.7. Connectors and Interfaces x
4.7.1. PCIe* Slot 4.7.2. ZQSFP+ 4.7.3. SFP+ 4.7.4. HDMI 4.7.5. SDI Port 4.7.6. MXP 4.7.7. Intel® FPGA Download Cable Direct Port (Debug Port) 4.7.8. FMC+ A/B Slot 4.7.9. FMC+ A/B LVDS Interfaces (LPC Pins) 4.7.10. LMK05028 Jitter Attenuator 4.7.11. FPGA-IOMAX10 Interface
4.8. Daughter Cards x
4.8.1. HPS IO-48 OOBE Daughter Card 4.8.2. HPS IO-48 NAND Flash Daughter Card 4.8.3. HPS Boot Flash Card
4.8.3. HPS Boot Flash Card x
4.8.3.1. Boot QSPI Flash Daughter Card 4.8.3.2. Boot MicroSD Daughter Card 4.8.3.3. Boot eMMC Daughter Card
4.9. System Memory x
4.9.1. FPGA Memory (DDR4 SO-DIMM) 4.9.2. HPS Memory (External 4 GB HILO x72 DDR4) 4.9.3. HPS I2C Interface
4.10. System Power x
4.10.1. Power Supply Options 4.10.2. Power Sequence 4.10.3. Power Distribution Network
5. Board Test System x
5.1. Preparing the Board 5.2. Running the BTS 5.3. Using the BTS
5.3. Using the BTS x
5.3.1. The Configure Menu 5.3.2. The GPIO Tab 5.3.3. The QSFP/SFP Tab 5.3.4. The PCIE Tab 5.3.5. The MXP Tab 5.3.6. The FMCA Tab 5.3.7. The FMCB Tab 5.3.8. The DDR4 Tab 5.3.9. Power Monitor 5.3.10. The Clock Control
A. Additional Information x
A.1. Modify the Stratix® 10 SX SoC Development Kit to use a battery for the BBRAM A.2. Modify the Stratix® 10 SX SoC Development Kit HPS DDR4 memory width and ECC configuration using the Golden Hardware Reference Design project A.3. Safety and Regulatory Information A.4. Compliance Information
A.3. Safety and Regulatory Information x
A.3.1. Safety Warnings A.3.2. Safety Cautions
A.4. Compliance Information x
A.4.1. Compliance and Conformity Statements
1. Overview
2. Getting Started
3. Development Kit Setup
4. Development Kit Components
5. Board Test System
A. Additional Information
B. Document Revision History for the Stratix® 10 10 SX SoC Development Kit User Guide

4.7.10. LMK05028 Jitter Attenuator

The LMK05028 device is a high-performance clock generator, jitter cleaner, and clock synchronizer with advanced reference clock selection and hitless switching to meet the stringent requirements of communications infrastructure applications.

The ultra-low jitter reduces bit error rates (BER) in high-speed serial links and improves signal to noise ratio (SNR) when clocking high-speed data converters.

The device has two independent PLL cores that can each synchronize or lock to one of four reference clock inputs, and the LMK05028 can generate up to eight output clocks with up to six different frequencies.

You can use the FPGA I2C port at FPGA pins BC25, BC26 to control LMK05028. LMK05028 3.3V I/O signals are connected to System MAX10 (U43) IO ports. You need to write code to connect these I/Os to FPGA 1.8V I/O ports. The J21 10-pin Header is used to connect the TI 05028 GUI port. You can use it to configure LMK05028.

Clock outputs from I/O ports (AW35, AW34, BA34, and AY34 pins) in 2B bank are connected to TI LMK05028.

The following table lists the cleaner output signal pin assignments:
Table 23.  LMK05028 Clock Cleaner Output Pin Frequencies and Pin Assignments
Output Frequency Pin Assignments
0 245 MHz or 297/1.001 MHz AF9, AF10 in 4E Bank
1 122.88 MHz Y38, Y37 in 1K Bank
2 122.88 MHz AT41, AT40 in 1C Bank
3 122.88 MHz D8, D9 (FALAP1, FALAN1) in FMCA
4 122.88 MHz D8, D9 (FBLAP1, FBLAN1) in FMCB
5 122.88 MHz AK12, AK 13 in 4E Bank
6 297 MHz AK12, AK 13 in 4E Bank
7 644.53125 MHz P9, P10 in bank 4M

TI LMH1983 is used to generate SDI reference clocks. Four 3.3V IO signals (U43 pins: E17, F17, B21, B22) in the MAX10 system controller are connected to the LMH1983 FIN, VIN, HIN and INIT input pins. SDI users need to write code to map the four 3.3V IOs to the FGPA 1.8V IOs. The 27 MHz output clock is directly connected to clock cleaner input 2. The 148.5 MHz clock is connected to U15AN28 and An27 in IO bank 2F. The clock cleaner application can be found at this link.

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