Stratix® 10 SX SoC Development Kit User Guide

Download PDF
ID 683303
Date 6/06/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Development Kit Components 5. Board Test System A. Additional Information B. Document Revision History for the Stratix® 10 10 SX SoC Development Kit User Guide
1. Overview x
1.1. General Development Kit Description 1.2. Recommended Operating Conditions 1.3. Handling the Development Kit
2. Getting Started x
2.1. Installing Quartus® Prime Software 2.2. Installing the Intel® FPGA Download Cable 2.3. Installing the Intel SoC Embedded Development Suite (EDS) 2.4. Installing the Stratix® 10 SX SoC Development Kit Package
3. Development Kit Setup x
3.1. Inspect the Development Kit 3.2. Default Setup of the Development Kit 3.3. MAX® 10 System Controller Updates
4. Development Kit Components x
4.1. Development Kit Feature Summary 4.2. Board Components 4.3. Stratix® 10 SoC Device Overview 4.4. MAX® 10 System Controller Overview 4.5. FPGA Configuration 4.6. General User Input/Output 4.7. Connectors and Interfaces 4.8. Daughter Cards 4.9. System Memory 4.10. System Power
4.7. Connectors and Interfaces x
4.7.1. PCIe* Slot 4.7.2. ZQSFP+ 4.7.3. SFP+ 4.7.4. HDMI 4.7.5. SDI Port 4.7.6. MXP 4.7.7. Intel® FPGA Download Cable Direct Port (Debug Port) 4.7.8. FMC+ A/B Slot 4.7.9. FMC+ A/B LVDS Interfaces (LPC Pins) 4.7.10. LMK05028 Jitter Attenuator 4.7.11. FPGA-IOMAX10 Interface
4.8. Daughter Cards x
4.8.1. HPS IO-48 OOBE Daughter Card 4.8.2. HPS IO-48 NAND Flash Daughter Card 4.8.3. HPS Boot Flash Card
4.8.3. HPS Boot Flash Card x
4.8.3.1. Boot QSPI Flash Daughter Card 4.8.3.2. Boot MicroSD Daughter Card 4.8.3.3. Boot eMMC Daughter Card
4.9. System Memory x
4.9.1. FPGA Memory (DDR4 SO-DIMM) 4.9.2. HPS Memory (External 4 GB HILO x72 DDR4) 4.9.3. HPS I2C Interface
4.10. System Power x
4.10.1. Power Supply Options 4.10.2. Power Sequence 4.10.3. Power Distribution Network
5. Board Test System x
5.1. Preparing the Board 5.2. Running the BTS 5.3. Using the BTS
5.3. Using the BTS x
5.3.1. The Configure Menu 5.3.2. The GPIO Tab 5.3.3. The QSFP/SFP Tab 5.3.4. The PCIE Tab 5.3.5. The MXP Tab 5.3.6. The FMCA Tab 5.3.7. The FMCB Tab 5.3.8. The DDR4 Tab 5.3.9. Power Monitor 5.3.10. The Clock Control
A. Additional Information x
A.1. Modify the Stratix® 10 SX SoC Development Kit to use a battery for the BBRAM A.2. Modify the Stratix® 10 SX SoC Development Kit HPS DDR4 memory width and ECC configuration using the Golden Hardware Reference Design project A.3. Safety and Regulatory Information A.4. Compliance Information
A.3. Safety and Regulatory Information x
A.3.1. Safety Warnings A.3.2. Safety Cautions
A.4. Compliance Information x
A.4.1. Compliance and Conformity Statements
1. Overview
2. Getting Started
3. Development Kit Setup
4. Development Kit Components
5. Board Test System
A. Additional Information
B. Document Revision History for the Stratix® 10 10 SX SoC Development Kit User Guide

B. Document Revision History for the Stratix® 10 10 SX SoC Development Kit User Guide

Document Version Changes
2024.06.06
  • Updated Table: Development Kit Version Information to remove development kit version information for Stratix® 10 SX SoC L-Tile.
  • Updated the HPS Memory (External 4 GB HILO x72 DDR4) section.
  • Made editorial edits throughout the document.
2023.06.02
  • Updated Figure: Board Picture (Top View).
  • Updated the HPS HILO Memory Connector board reference from J134 to J13 in Table: Stratix® 10 SoC Board Components.
  • Minor editorial edits.
2021.06.04 Updated Figure: HPS I2C Interface.
2020.09.08
Sections Updated:
  • Overview
  • Installing the SoC Embedded Development Suite (EDS)
  • Development Kit Feature Summary
  • Stratix® 10 SoC Device Overview
  • HPS Memory (External 4 GB HILO x72 DDR4)
2020.04.10 Sections Updated:
  • Overview
  • Installing Quartus® Prime Software
  • Installing the Intel® FPGA Download Cable
  • Installing the Intel SoC Embedded Development Suite (EDS)
  • Inspect the Development Kit
  • Development Kit Feature Summary
  • Board Components
  • HPS IO-48 OOBE Daughter Card
  • HPS IO-48 NAND Flash Daughter Card
  • Boot QSPI Flash Daughter Card
  • Boot MicroSD Daughter Card
  • HPS Memory (External 4 GB HILO x72 DDR4)
2019.09.20
Added sections:
  • Modify the Stratix® 10 SX SoC Development Kit to use a battery for the BBRAM
  • Modify the Stratix® 10 SX SoC Development Kit HPS DDR4 memory width and ECC configuration using the Golden Hardware Reference Design project
  • Installing the Stratix® 10 SX SoC Development Kit Package
  • MAX® 10 System Controller Updates
Document Version Changes
2019.03.20 Removed reference to an internal daughter card.
2018.09.20

Removed references to NAND x8 Configuration in FPGA Configuration.

2018.08.06

SDM Support of NAND dropped. Removed references to SDM Boot NAND Flash Daughter Card.

Updated these sections:
  • Inspect the Development Kit
  • Development Kit Feature Summary
  • HPS Boot Flash Card
2018.07.20 Added device variant SX in the document title.
2018.04.04 Initial Release.
Level Two Title