Stratix® 10 SX SoC Development Kit User Guide

ID 683303
Date 6/06/2024
Public
Document Table of Contents

4.7.7. Intel® FPGA Download Cable Direct Port (Debug Port)

The Direct Port is connected to the 3B bank.

Table 19.  Debug Port FPGA Pin Map
Pin Name Schematic Signal Name Description
PIN_AP16 USB0 USB Debug Data
PIN_AP15 USB1 USB Debug Data
PIN_AU13 USB2 USB Debug Data
PIN_AV13 USB3 USB Debug Data
PIN_AU12 USB4 USB Debug Data
PIN_AT12 USB5 USB Debug Data
PIN_AR13 USB6 USB Debug Data
PIN_AP12 USB7 USB Debug Data
PIN_AP14 USB_RDN USB Debug Control Signal
PIN_AP13 USB_WRN USB Debug Control Signal
PIN_AT14 USB_OEN USB Debug Control Signal
PIN_AR14 USB_RESETN USB Debug Control Signal
PIN_AR18 USB_EMPTY USB Debug Control Signal
PIN_AP18 USB_FULL USB Debug Control Signal
PIN_AU14 USB_SDA USB Debug I2C
PIN_AU15 USB_SCL USB Debug I2C