Stratix® 10 SX SoC Development Kit User Guide

Download PDF
ID 683303
Date 6/06/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Development Kit Components 5. Board Test System A. Additional Information B. Document Revision History for the Stratix® 10 10 SX SoC Development Kit User Guide
1. Overview x
1.1. General Development Kit Description 1.2. Recommended Operating Conditions 1.3. Handling the Development Kit
2. Getting Started x
2.1. Installing Quartus® Prime Software 2.2. Installing the Intel® FPGA Download Cable 2.3. Installing the Intel SoC Embedded Development Suite (EDS) 2.4. Installing the Stratix® 10 SX SoC Development Kit Package
3. Development Kit Setup x
3.1. Inspect the Development Kit 3.2. Default Setup of the Development Kit 3.3. MAX® 10 System Controller Updates
4. Development Kit Components x
4.1. Development Kit Feature Summary 4.2. Board Components 4.3. Stratix® 10 SoC Device Overview 4.4. MAX® 10 System Controller Overview 4.5. FPGA Configuration 4.6. General User Input/Output 4.7. Connectors and Interfaces 4.8. Daughter Cards 4.9. System Memory 4.10. System Power
4.7. Connectors and Interfaces x
4.7.1. PCIe* Slot 4.7.2. ZQSFP+ 4.7.3. SFP+ 4.7.4. HDMI 4.7.5. SDI Port 4.7.6. MXP 4.7.7. Intel® FPGA Download Cable Direct Port (Debug Port) 4.7.8. FMC+ A/B Slot 4.7.9. FMC+ A/B LVDS Interfaces (LPC Pins) 4.7.10. LMK05028 Jitter Attenuator 4.7.11. FPGA-IOMAX10 Interface
4.8. Daughter Cards x
4.8.1. HPS IO-48 OOBE Daughter Card 4.8.2. HPS IO-48 NAND Flash Daughter Card 4.8.3. HPS Boot Flash Card
4.8.3. HPS Boot Flash Card x
4.8.3.1. Boot QSPI Flash Daughter Card 4.8.3.2. Boot MicroSD Daughter Card 4.8.3.3. Boot eMMC Daughter Card
4.9. System Memory x
4.9.1. FPGA Memory (DDR4 SO-DIMM) 4.9.2. HPS Memory (External 4 GB HILO x72 DDR4) 4.9.3. HPS I2C Interface
4.10. System Power x
4.10.1. Power Supply Options 4.10.2. Power Sequence 4.10.3. Power Distribution Network
5. Board Test System x
5.1. Preparing the Board 5.2. Running the BTS 5.3. Using the BTS
5.3. Using the BTS x
5.3.1. The Configure Menu 5.3.2. The GPIO Tab 5.3.3. The QSFP/SFP Tab 5.3.4. The PCIE Tab 5.3.5. The MXP Tab 5.3.6. The FMCA Tab 5.3.7. The FMCB Tab 5.3.8. The DDR4 Tab 5.3.9. Power Monitor 5.3.10. The Clock Control
A. Additional Information x
A.1. Modify the Stratix® 10 SX SoC Development Kit to use a battery for the BBRAM A.2. Modify the Stratix® 10 SX SoC Development Kit HPS DDR4 memory width and ECC configuration using the Golden Hardware Reference Design project A.3. Safety and Regulatory Information A.4. Compliance Information
A.3. Safety and Regulatory Information x
A.3.1. Safety Warnings A.3.2. Safety Cautions
A.4. Compliance Information x
A.4.1. Compliance and Conformity Statements
1. Overview
2. Getting Started
3. Development Kit Setup
4. Development Kit Components
5. Board Test System
A. Additional Information
B. Document Revision History for the Stratix® 10 10 SX SoC Development Kit User Guide

4.2. Board Components

Figure 3. Board Picture (Top View)
Figure 4. Board Picture (Bottom View)

Board Components Table

Table 5.   Stratix® 10 SoC Board Components Table
Board Reference Type Description
Featured Device
U15 FPGA

Stratix® 10 SoC FPGA

U43 CPLD MAX® 10 10M50DAF484I7G System Controller
U46 CPLD MAX® 10 10M16SAU169C8G Power Manager CPLD
Configuration, Status and Setup Elements
J1 JTAG chain header Provides access to the JTAG chain and disables the on-board Intel® FPGA Download Cable II when using an external JTAG debugger such as an Intel® FPGA Download Cable II
SW1 JTAG chain control DIP switch Remove or include devices in the active JTAG chain
SW2 MSEL DIP Switch Controls the configuration scheme on the board. MSEL pin 0,1,2 connect to the DIP Switch
J57 Micro-USB Header USB interface to on-board Intel® FPGA Download Cable II JTAG for programming and debugging HPS, FPGA or MAX® 10 CPLD through a type-B Micro-USB cable.
SW4 Function DIP Switch Selects I2C master, controls PCIe* slot power and selects FPGA image source
SW8 Power Switch

ON position: Power GUI

OFF position: Intel® Enpirion® dongle

S2 Program select push button Toggles the program select LEDs which selects the program image that loads from flash memory to the FPGA
S1 Configure push button Load image from flash memory to the FPGA based on the settings of the program select LEDs
D22 Configuration done LED Illuminates when the FPGA is configured
D20 Load LED Illuminates when the MAX® 10 CPLD System Controller
D19 Error LED Illuminates when the FPGA configuration from flash memory fails
D31 Power LED Illuminates when 3.3V power is present
D1, D2 JTAG TX/RX LEDs Indicates the transmit or receive activity of the JTAG chain. The TX and RX LEDs flicker if the link is in use and active. The LEDs are either off when not in use or on when in use but idle
D24, D26, D28 Program select LEDs Illuminates to show which flash memory image loads to the FPGA when you press the program select push button
D29, D30 FMC port present LEDs Illuminates when a daughtercard is plugged into the FMC port
Clock Circuits
U26 Multi-output oscillator Si5338A quad-output fixed oscillator with 148.5 MHz, 100 MHz, 27 MHz and 100 MHz outputs
U29 50-MHz oscillator 50 MHz crystal oscillator for general purpose logic
U25 Multi-output oscillator Two 100 MHz outputs for PCIe* application
J19, J20 Clock input SMA connector External clock inputs for the transceiver test port
U33 Multi-output oscillator Si5341 ten-output fixed oscillator
U31 Multi-output oscillator Si5338A quad-output fixed oscillator with four 133.33 MHz outputs
U34 Multi-output clock cleaner LMK05028 Clock Cleaner
General User Input/Output
D21, D23, D25, D27 User LEDs Four user LEDs. Illuminate when driven high.
SW3 User DIP Switch User DIP switch. When the switch is ON, a logic 0 is selected
S3 FPGA Reset Push Button Reset the FPGA logic
S4, S5, S6, S7 General user push buttons Four user push buttons. Driven low when pressed
S20 HPS Reset Push Buttons HPS cold/warm reset push buttons
Memory Connectors
J13 HPS HILO Memory Connector HPS memory card include DDR3 HILO memory card and DDR4 HILO memory card
J14 Boot Flash Connector Boot flash card options include QSPI flash card, SD micro flash card
J28 SO-DIMM 16 GB SO-DIMM DDR4 Memory Card
U41 I2C EEPROM 32 Kb I2C serial EEPROM
Communication Ports
J53 PCIe* socket Gen3 x16 Socket
J11, J12 FMC Port J29 is a V57.4 compatible FMC connector. J19 is a FMC connector defined by Intel® 16 transceivers specification
J7 SFP+ Port One SFP+ Ports
J3 Gigabit Ethernet Port SGMII Gigabit Ethernet port through FPGA transceiver
J4 Gigabit Ethernet Port SGMII Gigabit Ethernet Port through FPGA transceiver
J9-J10 QSFP28 Optical Transceiver Interface 17 Gbps/28 Gbps, 8 channels connected to QSFP28 modules
J57, U2 USB-UART Port Mini-B USB interface to USB-to-UART bridge for serial UART interface
J22 DB9 UART Port DB9 RS-232 UART Port
U42 Real-time clock DS1339 device with built-in power sense circuit that detects power failures and automatically switches to backup battery supply, maintaining time keeping even when the board is not powered
Video and Display Ports
J8 HDMI Port Display Port interface
J5, U13 SDI Video Output Port HDBNC 75-Ohm SDI video TX interface
J6, U14 SDI Video Input Port HDBNC 75-Ohm SDI video RX interface
J29 Power GUI Connector Intel® Enpirion® Power GUI Connector
Power Supply
J25, J55 DC input jack Accepts 12 V DC power supply
SW7 Power Switch Switch to power on or off the board when power is supplied from the DC input jack
Level Two Title