Stratix® 10 SX SoC Development Kit User Guide

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ID 683303
Date 6/06/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Development Kit Components 5. Board Test System A. Additional Information B. Document Revision History for the Stratix® 10 10 SX SoC Development Kit User Guide
1. Overview x
1.1. General Development Kit Description 1.2. Recommended Operating Conditions 1.3. Handling the Development Kit
2. Getting Started x
2.1. Installing Quartus® Prime Software 2.2. Installing the Intel® FPGA Download Cable 2.3. Installing the Intel SoC Embedded Development Suite (EDS) 2.4. Installing the Stratix® 10 SX SoC Development Kit Package
3. Development Kit Setup x
3.1. Inspect the Development Kit 3.2. Default Setup of the Development Kit 3.3. MAX® 10 System Controller Updates
4. Development Kit Components x
4.1. Development Kit Feature Summary 4.2. Board Components 4.3. Stratix® 10 SoC Device Overview 4.4. MAX® 10 System Controller Overview 4.5. FPGA Configuration 4.6. General User Input/Output 4.7. Connectors and Interfaces 4.8. Daughter Cards 4.9. System Memory 4.10. System Power
4.7. Connectors and Interfaces x
4.7.1. PCIe* Slot 4.7.2. ZQSFP+ 4.7.3. SFP+ 4.7.4. HDMI 4.7.5. SDI Port 4.7.6. MXP 4.7.7. Intel® FPGA Download Cable Direct Port (Debug Port) 4.7.8. FMC+ A/B Slot 4.7.9. FMC+ A/B LVDS Interfaces (LPC Pins) 4.7.10. LMK05028 Jitter Attenuator 4.7.11. FPGA-IOMAX10 Interface
4.8. Daughter Cards x
4.8.1. HPS IO-48 OOBE Daughter Card 4.8.2. HPS IO-48 NAND Flash Daughter Card 4.8.3. HPS Boot Flash Card
4.8.3. HPS Boot Flash Card x
4.8.3.1. Boot QSPI Flash Daughter Card 4.8.3.2. Boot MicroSD Daughter Card 4.8.3.3. Boot eMMC Daughter Card
4.9. System Memory x
4.9.1. FPGA Memory (DDR4 SO-DIMM) 4.9.2. HPS Memory (External 4 GB HILO x72 DDR4) 4.9.3. HPS I2C Interface
4.10. System Power x
4.10.1. Power Supply Options 4.10.2. Power Sequence 4.10.3. Power Distribution Network
5. Board Test System x
5.1. Preparing the Board 5.2. Running the BTS 5.3. Using the BTS
5.3. Using the BTS x
5.3.1. The Configure Menu 5.3.2. The GPIO Tab 5.3.3. The QSFP/SFP Tab 5.3.4. The PCIE Tab 5.3.5. The MXP Tab 5.3.6. The FMCA Tab 5.3.7. The FMCB Tab 5.3.8. The DDR4 Tab 5.3.9. Power Monitor 5.3.10. The Clock Control
A. Additional Information x
A.1. Modify the Stratix® 10 SX SoC Development Kit to use a battery for the BBRAM A.2. Modify the Stratix® 10 SX SoC Development Kit HPS DDR4 memory width and ECC configuration using the Golden Hardware Reference Design project A.3. Safety and Regulatory Information A.4. Compliance Information
A.3. Safety and Regulatory Information x
A.3.1. Safety Warnings A.3.2. Safety Cautions
A.4. Compliance Information x
A.4.1. Compliance and Conformity Statements
1. Overview
2. Getting Started
3. Development Kit Setup
4. Development Kit Components
5. Board Test System
A. Additional Information
B. Document Revision History for the Stratix® 10 10 SX SoC Development Kit User Guide

4.7.9. FMC+ A/B LVDS Interfaces (LPC Pins)

All LVDS interface signals except the LAP/N33, LAP/N32 signals from FMC+ A are directly connected to FPGA I/O ports. For the PCIE ED port application, PCIEA_EP_PERSTn and PCIEA_WAKEN are connected to System MAX10 IO through LAP/N33 signals.

LAP/N32 signals are shorted together into PCIE_present. All LA P/N except LAP/N33, LAP/N32 signals from FMC+B are directly connected to FPGA I/O ports. For a PCIE ED port application, PCIEA_EP_PERSTn and PCIEA_WAKEN are connected to System MAX10 I/O through FALP/N33 signals. LP/N32 signals are short together into PCIE_present.

Most HB and HA signals from FMC+B are connected to System MAX10 I/O. You must write the code to map these signals to the I/O ports of FPGA.

Table 22.  FMC+ A/B Port FPGA Map
Pin Name Schematic Signal Name Description
PIN_AP21 FALAN20 FMCA LA LVDS
PIN_AN21 FALAP20 FMCA LA LVDS
PIN_BG20 FALAN25 FMCA LA LVDS
PIN_BF20 FALAP25 FMCA LA LVDS
PIN_BD18 FALAN19 FMCA LA LVDS
PIN_BE18 FALAP19 FMCA LA LVDS
PIN_BG19 FALAN21 FMCA LA LVDS
PIN_BG18 FALAP21 FMCA LA LVDS
PIN_BH21 FALAN24 FMCA LA LVDS
PIN_BH20 FALAP24 FMCA LA LVDS
PIN_BH17 FALAN18 FMCA LA LVDS
PIN_BG17 FALAP18 FMCA LA LVDS
PIN_BJ20 FALAN27 FMCA LA LVDS
PIN_BJ19 FALAP27 FMCA LA LVDS
PIN_BJ18 FALAN26 FMCA LA LVDS
PIN_BH18 FALAP26 FMCA LA LVDS
PIN_AT16 FALAN11 FMCA LA LVDS
PIN_AT15 FALAP11 FMCA LA LVDS
PIN_AN18 FALAN15 FMCA LA LVDS
PIN_AN17 FALAP15 FMCA LA LVDS
PIN_AU17 FALAN17 FMCA LA LVDS
PIN_AT17 FALAP17 FMCA LA LVDS
PIN_AU28 FALAN12 FMCA LA LVDS
PIN_AU29 FALAP12 FMCA LA LVDS
PIN_BA30 FALAN9 FMCA LA LVDS
PIN_BA31 FALAP9 FMCA LA LVDS
PIN_BC32 FALAN3 FMCA LA LVDS
PIN_BC31 FALAP3 FMCA LA LVDS
PIN_AW31 FALAN0 FMCA LA LVDS
PIN_AW30 FALAP0 FMCA LA LVDS
PIN_BD31 FA_LA_DEVCLK_N FMCA LA LVDS
PIN_BE31 FA_LA_DEVCLK_P FMCA LA LVDS
PIN_BF30 FALAN6 FMCA LA LVDS
PIN_BF31 FALAP6 FMCA LA LVDS
PIN_BD30 FALAN4 FMCA LA LVDS
PIN_BC30 FALAP4 FMCA LA LVDS
PIN_BH30 FALAN5 FMCA LA LVDS
PIN_BG30 FALAP5 FMCA LA LVDS
PIN_BF32 FALAN7 FMCA LA LVDS
PIN_BE32 FALAP7 FMCA LA LVDS
PIN_BG32 FALAN8 FMCA LA LVDS
PIN_BH32 FALAP8 FMCA LA LVDS
PIN_BD36 FALAN31 FMCA LA LVDS
PIN_BE36 FALAP31 FMCA LA LVDS
PIN_BC35 FALAN23 FMCA LA LVDS
PIN_BC36 FALAP23 FMCA LA LVDS
PIN_BB34 FALAN10 FMCA LA LVDS
PIN_BB33 FALAP10 FMCA LA LVDS
PIN_BF35 FALAN29 FMCA LA LVDS
PIN_BF36 FALAP29 FMCA LA LVDS
PIN_BG35 FALAN32_FPGA FMCA LA LVDS
PIN_BH35 FALAP32_FPGA FMCA LA LVDS
PIN_BE34 FALAN33_FPGA FMCA LA LVDS
PIN_BE33 FALAP33_FPGA FMCA LA LVDS
PIN_BJ36 FALAN22 FMCA LA LVDS
PIN_BJ35 FALAP22 FMCA LA LVDS
PIN_AT32 FALAN14 FMCA LA LVDS
PIN_AU32 FALAP14 FMCA LA LVDS
PIN_AU35 FALAN30 FMCA LA LVDS
PIN_AV35 FALAP30 FMCA LA LVDS
PIN_AY13 FAHAN14 FMCA HA LVDS
PIN_AW13 FAHAP14 FMCA HA LVDS
PIN_AV12 FAHAN18 FMCA HA LVDS
PIN_AV11 FAHAP18 FMCA HA LVDS
PIN_AY12 FAHAN20 FMCA HA LVDS
PIN_BA12 FAHAP20 FMCA HA LVDS
PIN_BA11 FAHAN21 FMCA HA LVDS
PIN_BA10 FAHAP21 FMCA HA LVDS
PIN_AW11 FAHAN17 FMCA HA LVDS
PIN_AY11 FAHAP17 FMCA HA LVDS
PIN_BB12 FAHAN0 FMCA HA LVDS
PIN_BC12 FAHAP0 FMCA HA LVDS
PIN_BB10 FAHAN1 FMCA HA LVDS
PIN_BC10 FAHAP1 FMCA HA LVDS
PIN_BB20 FAHAN2 FMCA HA LVDS
PIN_BC20 FAHAP2 FMCA HA LVDS
PIN_AY21 FAHAN11 FMCA HA LVDS
PIN_AW21 FAHAP11 FMCA HA LVDS
PIN_AW20 FAHAN10 FMCA HA LVDS
PIN_AW19 FAHAP10 FMCA HA LVDS
PIN_BA19 FAHAN15 FMCA HA LVDS
PIN_BB19 FAHAP15 FMCA HA LVDS
PIN_AU20 FAHAN19 FMCA HA LVDS
PIN_AT20 FAHAP19 FMCA HA LVDS
PIN_BD20 FAHAN6 FMCA HA LVDS
PIN_BD19 FAHAP6 FMCA HA LVDS
PIN_BB18 FAHAN23 FMCA HA LVDS
PIN_BC18 FAHAP23 FMCA HA LVDS
PIN_AV20 FAHAN16 FMCA HA LVDS
PIN_AV21 FAHAP16 FMCA HA LVDS
PIN_BF17 FAHAN22 FMCA HA LVDS
PIN_BE17 FAHAP22 FMCA HA LVDS
PIN_AV28 FAHAN12 FMCA HA LVDS
PIN_AW28 FAHAP12 FMCA HA LVDS
PIN_AV30 FAHAN5 FMCA HA LVDS
PIN_AU30 FAHAP5 FMCA HA LVDS
PIN_AY32 FAHAN9 FMCA HA LVDS
PIN_AY31 FAHAP9 FMCA HA LVDS
PIN_BE29 FAHAN7 FMCA HA LVDS
PIN_BD29 FAHAP7 FMCA HA LVDS
PIN_BJ31 FAHAN13 FMCA HA LVDS
PIN_BH31 FAHAP13 FMCA HA LVDS
PIN_BB29 FAHAN3 FMCA HA LVDS
PIN_BB30 FAHAP3 FMCA HA LVDS
PIN_AV32 FAHAN4 FMCA HA LVDS
PIN_AV33 FAHAP4 FMCA HA LVDS
PIN_BF19 FAHBN1 FMCA HB LVDS
PIN_BE19 FAHBP1 FMCA HB LVDS
PIN_AR16 FAHBN16 FMCA HB LVDS
PIN_AR17 FAHBP16 FMCA HB LVDS
PIN_BB25 FAHBN6 FMCA HB LVDS
PIN_BA25 FAHBP6 FMCA HB LVDS
PIN_BB27 FAHBN19 FMCA HB LVDS
PIN_BC27 FAHBP19 FMCA HB LVDS
PIN_AW29 FAHBN2 FMCA HB LVDS
PIN_AY29 FAHBP2 FMCA HB LVDS
PIN_BB28 FAHBN3 FMCA HB LVDS
PIN_BA29 FAHBP3 FMCA HB LVDS
PIN_AT30 FAHBN0 FMCA HB LVDS
PIN_AT29 FAHBP0 FMCA HB LVDS
PIN_BB32 FAHBN5 FMCA HB LVDS
PIN_BA32 FAHBP5 FMCA HB LVDS
PIN_BG28 FAHBN15 FMCA HB LVDS
PIN_BG29 FAHBP15 FMCA HB LVDS
PIN_BE28 FAHBN10 FMCA HB LVDS
PIN_BF29 FAHBP10 FMCA HB LVDS
PIN_BJ29 FAHBN14 FMCA HB LVDS
PIN_BJ30 FAHBP14 FMCA HB LVDS
PIN_BH28 FAHBN18 FMCA HB LVDS
PIN_BJ28 FAHBP18 FMCA HB LVDS
PIN_BD35 FAHBN4 FMCA HB LVDS
PIN_BD34 FAHBP4 FMCA HB LVDS
PIN_BC33 FAHAN8 FMCA HB LVDS
PIN_BD33 FAHAP8 FMCA HB LVDS
PIN_AY33 FAHBN8 FMCA HB LVDS
PIN_AW33 FAHBP8 FMCA HB LVDS
PIN_BA35 FAHBN21 FMCA HB LVDS
PIN_BB35 FAHBP21 FMCA HB LVDS
PIN_AY36 FAHBN20 FMCA HB LVDS
PIN_BA36 FAHBP20 FMCA HB LVDS
PIN_BF34 FAHBN12 FMCA HB LVDS
PIN_BG34 FAHBP12 FMCA HB LVDS
PIN_BJ34 FAHBN9 FMCA HB LVDS
PIN_BJ33 FAHBP9 FMCA HB LVDS
PIN_AT34 FAHBN11 FMCA HB LVDS
PIN_AT35 FAHBP11 FMCA HB LVDS
PIN_AR31 FAHBN7 FMCA HB LVDS
PIN_AR32 FAHBP7 FMCA HB LVDS
PIN_AU33 FAHBN17 FMCA HB LVDS
PIN_AU34 FAHBP17 FMCA HB LVDS
PIN_AT19 FACLK1M2CN FMCA M2C Clk1N
PIN_AR19 FACLK1M2CP FMCA M2C Clk1P
PIN_BE21 FACLK0M2CN FMCA M2C Clk0N
PIN_BF21 FACLK0M2CP FMCA M2C Clk0P
PIN_AY17 FACLKDIR FMCA CLK DIR
PIN_AY40 FBLAN3 FMCB LA LVDS
PIN_BA40 FBLAP3 FMCB LA LVDS
PIN_BA39 FBLAN20 FMCB LA LVDS
PIN_BB39 FBLAP20 FMCB LA LVDS
PIN_BB40 FBLAN11 FMCB LA LVDS
PIN_BC40 FBLAP11 FMCB LA LVDS
PIN_BD38 FBLAN12 FMCB LA LVDS
PIN_BD39 FBLAP12 FMCB LA LVDS
PIN_BC38 FBLAN15 FMCB LA LVDS
PIN_BB38 FBLAP15 FMCB LA LVDS
PIN_BC37 FBLAN27 FMCB LA LVDS
PIN_BB37 FBLAP27 FMCB LA LVDS
PIN_BD40 FBLAN8 FMCB LA LVDS
PIN_BE40 FBLAP8 FMCB LA LVDS
PIN_BG38 FBLAN2 FMCB LA LVDS
PIN_BG37 FBLAP2 FMCB LA LVDS
PIN_BE38 FBLAN4 FMCB LA LVDS
PIN_BE39 FBLAP4 FMCB LA LVDS
PIN_BE37 FBLAN16 FMCB LA LVDS
PIN_BF37 FBLAP16 FMCB LA LVDS
PIN_BF39 FBLAN7 FMCB LA LVDS
PIN_BF40 FBLAP7 FMCB LA LVDS
PIN_BH37 FBLAN0 FMCB LA LVDS
PIN_BH36 FBLAP0 FMCB LA LVDS
PIN_AW39 FB_LA_DEVCLK_N FMCB LA LVDS
PIN_AW38 FB_LA_DEVCLK_P FMCB LA LVDS
PIN_BA37 FBLAN22 FMCB LA LVDS
PIN_AY37 FBLAP22 FMCB LA LVDS
PIN_AV40 FBLAN9 FMCB LA LVDS
PIN_AW40 FBLAP9 FMCB LA LVDS
PIN_AY39 FBLAN19 FMCB LA LVDS
PIN_AY38 FBLAP19 FMCB LA LVDS
PIN_AU37 FAHBN13 FMCB LA LVDS
PIN_AU38 FAHBP13 FMCB LA LVDS
PIN_AV38 FBLAN26 FMCB LA LVDS
PIN_AV37 FBLAP26 FMCB LA LVDS
PIN_AR34 FBLAN23 FMCB LA LVDS
PIN_AP35 FBLAP23 FMCB LA LVDS
PIN_AR36 FBLAN18 FMCB LA LVDS
PIN_AP36 FBLAP18 FMCB LA LVDS
PIN_AP33 FBLAN10 FMCB LA LVDS
PIN_AN33 FBLAP10 FMCB LA LVDS
PIN_AT36 FBLAN13 FMCB LA LVDS
PIN_AT37 FBLAP13 FMCB LA LVDS
PIN_AR37 FBLAN6 FMCB LA LVDS
PIN_AT38 FBLAP6 FMCB LA LVDS
PIN_AR33 FBLAN5 FMCB LA LVDS
PIN_AP34 FBLAP5 FMCB LA LVDS
PIN_AT25 FBLAN30 FMCB LA LVDS
PIN_AU25 FBLAP30 FMCB LA LVDS
PIN_AW25 FBLAN29 FMCB LA LVDS
PIN_AV25 FBLAP29 FMCB LA LVDS
PIN_AT26 FBLAN24 FMCB LA LVDS
PIN_AR26 FBLAP24 FMCB LA LVDS
PIN_AU27 FBLAN25 FMCB LA LVDS
PIN_AT27 FBLAP25 FMCB LA LVDS
PIN_AY26 FBLAN21 FMCB LA LVDS
PIN_AW26 FBLAP21 FMCB LA LVDS
PIN_AN26 FBLAN28 FMCB LA LVDS
PIN_AP26 FBLAP28 FMCB LA LVDS
PIN_AN25 FBLAN31 FMCB LA LVDS
PIN_AP25 FBLAP31 FMCB LA LVDS
PIN_AP29 FBLAN32_FPGA FMCB LA LVDS
PIN_AP28 FBLAP32_FPGA FMCB LA LVDS
PIN_AR27 FBLAN33_FPGA FMCB LA LVDS
PIN_AR28 FBLAP33_FPGA FMCB LA LVDS
PIN_AP31 FBLAN14 FMCB LA LVDS
PIN_AP30 FBLAP14 FMCB LA LVDS
PIN_BA26 FBLAN17 FMCB LA LVDS
PIN_BA27 FBLAP17 FMCB LA LVDS
Level Two Title