Stratix® 10 SX SoC Development Kit User Guide

ID 683303
Date 6/06/2024
Public
Document Table of Contents

4.6. General User Input/Output

Table 11.  User I/O Pin Map
Pin Name Schematic Signal Name Description
PIN_A24 USER_LED_FPGA0 USER_LED0
PIN_B24 USER_LED_FPGA2 USER_LED1
PIN_F22 USER_LED_FPGA1 USER_LED2
PIN_E22 USER_LED_FPGA3 USER_LED3
PIN_A26 USER_PB_FPGA0 USER_PB0
PIN_A25 USER_PB_FPGA1 USER_PB1
PIN_D23 USER_PB_FPGA2 USER_PB2
PIN_D24 USER_PB_FPGA3 USER_PB3
PIN_B23 USER_DIPSW_FPGA0 USER_DPSW0
PIN_C23 USER_DIPSW_FPGA1 USER_DPSW1
PIN_E23 USER_DIPSW_FPGA2 USER_DPSW2
PIN_E24 USER_DIPSW_FPGA3 USER_DPSW3