Stratix® 10 SX SoC Development Kit User Guide

ID 683303
Date 6/06/2024
Public
Document Table of Contents

4.5. FPGA Configuration

This development kit supports the following FPGA configurations:
  • QSPI Configuration
  • SDMMC x4 Configuration
  • JTAG Only

A 4-bit DIP Switch (SW2) is used to select the FPGA configuration mode.

Table 9.  DIP Switch Bits
Switch Bit Name
1 MSEL0
2 MSEL1
3 MSEL2
4 Not Used
Table 10.  DIP Switch Bit Description
MSEL2 MSEL1 MSEL0 Mode
OFF OFF ON QSPI
ON OFF OFF SDMMC x4, SDMMC x8
ON ON ON JTAG
Note: The default setting is JTAG mode. The default bit position is "ON, ON, ON, ON"