Stratix® 10 SX SoC Development Kit User Guide

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ID 683303
Date 6/06/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Development Kit Components 5. Board Test System A. Additional Information B. Document Revision History for the Stratix® 10 10 SX SoC Development Kit User Guide
1. Overview x
1.1. General Development Kit Description 1.2. Recommended Operating Conditions 1.3. Handling the Development Kit
2. Getting Started x
2.1. Installing Quartus® Prime Software 2.2. Installing the Intel® FPGA Download Cable 2.3. Installing the Intel SoC Embedded Development Suite (EDS) 2.4. Installing the Stratix® 10 SX SoC Development Kit Package
3. Development Kit Setup x
3.1. Inspect the Development Kit 3.2. Default Setup of the Development Kit 3.3. MAX® 10 System Controller Updates
4. Development Kit Components x
4.1. Development Kit Feature Summary 4.2. Board Components 4.3. Stratix® 10 SoC Device Overview 4.4. MAX® 10 System Controller Overview 4.5. FPGA Configuration 4.6. General User Input/Output 4.7. Connectors and Interfaces 4.8. Daughter Cards 4.9. System Memory 4.10. System Power
4.7. Connectors and Interfaces x
4.7.1. PCIe* Slot 4.7.2. ZQSFP+ 4.7.3. SFP+ 4.7.4. HDMI 4.7.5. SDI Port 4.7.6. MXP 4.7.7. Intel® FPGA Download Cable Direct Port (Debug Port) 4.7.8. FMC+ A/B Slot 4.7.9. FMC+ A/B LVDS Interfaces (LPC Pins) 4.7.10. LMK05028 Jitter Attenuator 4.7.11. FPGA-IOMAX10 Interface
4.8. Daughter Cards x
4.8.1. HPS IO-48 OOBE Daughter Card 4.8.2. HPS IO-48 NAND Flash Daughter Card 4.8.3. HPS Boot Flash Card
4.8.3. HPS Boot Flash Card x
4.8.3.1. Boot QSPI Flash Daughter Card 4.8.3.2. Boot MicroSD Daughter Card 4.8.3.3. Boot eMMC Daughter Card
4.9. System Memory x
4.9.1. FPGA Memory (DDR4 SO-DIMM) 4.9.2. HPS Memory (External 4 GB HILO x72 DDR4) 4.9.3. HPS I2C Interface
4.10. System Power x
4.10.1. Power Supply Options 4.10.2. Power Sequence 4.10.3. Power Distribution Network
5. Board Test System x
5.1. Preparing the Board 5.2. Running the BTS 5.3. Using the BTS
5.3. Using the BTS x
5.3.1. The Configure Menu 5.3.2. The GPIO Tab 5.3.3. The QSFP/SFP Tab 5.3.4. The PCIE Tab 5.3.5. The MXP Tab 5.3.6. The FMCA Tab 5.3.7. The FMCB Tab 5.3.8. The DDR4 Tab 5.3.9. Power Monitor 5.3.10. The Clock Control
A. Additional Information x
A.1. Modify the Stratix® 10 SX SoC Development Kit to use a battery for the BBRAM A.2. Modify the Stratix® 10 SX SoC Development Kit HPS DDR4 memory width and ECC configuration using the Golden Hardware Reference Design project A.3. Safety and Regulatory Information A.4. Compliance Information
A.3. Safety and Regulatory Information x
A.3.1. Safety Warnings A.3.2. Safety Cautions
A.4. Compliance Information x
A.4.1. Compliance and Conformity Statements
1. Overview
2. Getting Started
3. Development Kit Setup
4. Development Kit Components
5. Board Test System
A. Additional Information
B. Document Revision History for the Stratix® 10 10 SX SoC Development Kit User Guide

4.7.11. FPGA-IOMAX10 Interface

The I/O signals of the transceiver I/O banks and the 14 I/O ports in 3A banks are connected to System MAX® 10.

The figure below illustrates the signal connections between MAX® 10 and Stratix® 10 SX SoC. You can write your own code to map User I/O to these pins.

Figure 5. Signal Connections
Table 24.  FPGA-IOMAX10 Pin Map
Pin Name Schematic Signal Name Description
PIN_AJ34 NPERSTL0 System MAX10_IO
PIN_AG35 1V8_IO_MUX0 System MAX10_IO
PIN_AH33 1V8_IO_MUX1 System MAX10_IO
PIN_AF34 1V8_IO_MUX2 System MAX10_IO
PIN_AE36 1V8_IO_MUX3 System MAX10_IO
PIN_AG34 1V8_IO_MUX4 System MAX10_IO
PIN_AH32 1V8_IO_MUX5 System MAX10_IO
PIN_AJ33 1V8_IO_MUX6 System MAX10_IO
PIN_AD34 NPERSTL2 System MAX10_IO
PIN_AD35 1V8_IO_MUX7 System MAX10_IO
PIN_AC35 1V8_IO_MUX8 System MAX10_IO
PIN_AB34 1V8_IO_MUX9 System MAX10_IO
PIN_AC33 1V8_IO_MUX10 System MAX10_IO
PIN_AC36 1V8_IO_MUX11 System MAX10_IO
PIN_AB35 1V8_IO_MUX12 System MAX10_IO
PIN_AB36 1V8_IO_MUX13 System MAX10_IO
PIN_AH16 NPERSTR0 System MAX10_IO
PIN_AF15 1V8_IO_MUX14 System MAX10_IO
PIN_AB12 1V8_IO_MUX15 System MAX10_IO
PIN_AF17 1V8_IO_MUX16 System MAX10_IO
PIN_AD16 1V8_IO_MUX17 System MAX10_IO
PIN_AF16 1V8_IO_MUX18 System MAX10_IO
PIN_AE16 1V8_IO_MUX19 System MAX10_IO
PIN_AH17 1V8_IO_MUX20 System MAX10_IO
PIN_AE14 NPERSTR2 System MAX10_IO
PIN_AD15 1V8_IO_MUX21 System MAX10_IO
PIN_AC15 1V8_IO_MUX22 System MAX10_IO
PIN_AC14 1V8_IO_MUX23 System MAX10_IO
PIN_AB13 1V8_IO_MUX24 System MAX10_IO
PIN_AD14 1V8_IO_MUX25 System MAX10_IO
PIN_AB15 1V8_IO_MUX26 System MAX10_IO
PIN_AB14 1V8_IO_MUX27 System MAX10_IO
PIN_BD13 AVST_D0 System MAX10_IO
PIN_BE13 AVST_D1 System MAX10_IO
PIN_BF15 AVST_D2 System MAX10_IO
PIN_BG15 AVST_D3 System MAX10_IO
PIN_BE14 AVST_D4 System MAX10_IO
PIN_BF14 AVST_D5 System MAX10_IO
PIN_BE16 AVST_D6 System MAX10_IO
PIN_BF16 AVST_D7 System MAX10_IO
PIN_BD16 AVST_D8 System MAX10_IO
PIN_BC16 AVST_D9 System MAX10_IO
PIN_BD14 AVST_D10 System MAX10_IO
PIN_BD15 AVST_D11 System MAX10_IO
PIN_BF12 AVST_D12 System MAX10_IO
PIN_BG12 AVST_D13 System MAX10_IO
PIN_BJ13 AVST_D14 System MAX10_IO
PIN_BJ14 AVST_D15 System MAX10_IO
PIN_BG13 FPGA_MAX10_IO0 System MAX10_IO
PIN_BG14 FPGA_MAX10_IO1 System MAX10_IO
PIN_BH15 FPGA_MAX10_IO2 System MAX10_IO
PIN_BJ15 FPGA_MAX10_IO3 System MAX10_IO
PIN_BH12 ENETA_INTN_B System MAX10_IO
PIN_BH13 AVST_VALID System MAX10_IO
PIN_BH16 CLK_50M_FPGA System MAX10_IO
PIN_BJ16 FPGA_MAX10_IO5 System MAX10_IO
PIN_AV15 FPGA_MAX10_IO6 System MAX10_IO
PIN_AW15 FPGA_MAX10_IO7 System MAX10_IO
PIN_BA15 FPGA_MAX10_IO8 System MAX10_IO
PIN_BA16 FPGA_MAX10_IO9 System MAX10_IO
PIN_AW14 FPGA_MAX10_IO10 System MAX10_IO
PIN_AY14 FPGA_MAX10_IO11 System MAX10_IO
PIN_BB14 FPGA_MAX10_IO12 System MAX10_IO
PIN_BA14 FPGA_MAX10_IO13 System MAX10_IO
PIN_BB15 FPGA_MAX10_IO14 System MAX10_IO
PIN_BC15 GLOBAL_RESETN System MAX10_IO
PIN_BC13 FPGA_PR_REQUEST System MAX10_IO
PIN_BA17 FPGA_PR_DONE System MAX10_IO
PIN_AY16 FPGA_PR_ERROR System MAX10_IO
PIN_AY19 AVST_CLK System MAX10_IO
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