Stratix® 10 SX SoC Development Kit User Guide

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ID 683303
Date 6/06/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Development Kit Components 5. Board Test System A. Additional Information B. Document Revision History for the Stratix® 10 10 SX SoC Development Kit User Guide
1. Overview x
1.1. General Development Kit Description 1.2. Recommended Operating Conditions 1.3. Handling the Development Kit
2. Getting Started x
2.1. Installing Quartus® Prime Software 2.2. Installing the Intel® FPGA Download Cable 2.3. Installing the Intel SoC Embedded Development Suite (EDS) 2.4. Installing the Stratix® 10 SX SoC Development Kit Package
3. Development Kit Setup x
3.1. Inspect the Development Kit 3.2. Default Setup of the Development Kit 3.3. MAX® 10 System Controller Updates
4. Development Kit Components x
4.1. Development Kit Feature Summary 4.2. Board Components 4.3. Stratix® 10 SoC Device Overview 4.4. MAX® 10 System Controller Overview 4.5. FPGA Configuration 4.6. General User Input/Output 4.7. Connectors and Interfaces 4.8. Daughter Cards 4.9. System Memory 4.10. System Power
4.7. Connectors and Interfaces x
4.7.1. PCIe* Slot 4.7.2. ZQSFP+ 4.7.3. SFP+ 4.7.4. HDMI 4.7.5. SDI Port 4.7.6. MXP 4.7.7. Intel® FPGA Download Cable Direct Port (Debug Port) 4.7.8. FMC+ A/B Slot 4.7.9. FMC+ A/B LVDS Interfaces (LPC Pins) 4.7.10. LMK05028 Jitter Attenuator 4.7.11. FPGA-IOMAX10 Interface
4.8. Daughter Cards x
4.8.1. HPS IO-48 OOBE Daughter Card 4.8.2. HPS IO-48 NAND Flash Daughter Card 4.8.3. HPS Boot Flash Card
4.8.3. HPS Boot Flash Card x
4.8.3.1. Boot QSPI Flash Daughter Card 4.8.3.2. Boot MicroSD Daughter Card 4.8.3.3. Boot eMMC Daughter Card
4.9. System Memory x
4.9.1. FPGA Memory (DDR4 SO-DIMM) 4.9.2. HPS Memory (External 4 GB HILO x72 DDR4) 4.9.3. HPS I2C Interface
4.10. System Power x
4.10.1. Power Supply Options 4.10.2. Power Sequence 4.10.3. Power Distribution Network
5. Board Test System x
5.1. Preparing the Board 5.2. Running the BTS 5.3. Using the BTS
5.3. Using the BTS x
5.3.1. The Configure Menu 5.3.2. The GPIO Tab 5.3.3. The QSFP/SFP Tab 5.3.4. The PCIE Tab 5.3.5. The MXP Tab 5.3.6. The FMCA Tab 5.3.7. The FMCB Tab 5.3.8. The DDR4 Tab 5.3.9. Power Monitor 5.3.10. The Clock Control
A. Additional Information x
A.1. Modify the Stratix® 10 SX SoC Development Kit to use a battery for the BBRAM A.2. Modify the Stratix® 10 SX SoC Development Kit HPS DDR4 memory width and ECC configuration using the Golden Hardware Reference Design project A.3. Safety and Regulatory Information A.4. Compliance Information
A.3. Safety and Regulatory Information x
A.3.1. Safety Warnings A.3.2. Safety Cautions
A.4. Compliance Information x
A.4.1. Compliance and Conformity Statements
1. Overview
2. Getting Started
3. Development Kit Setup
4. Development Kit Components
5. Board Test System
A. Additional Information
B. Document Revision History for the Stratix® 10 10 SX SoC Development Kit User Guide

4.9.2. HPS Memory (External 4 GB HILO x72 DDR4)

The 72-bit HPS DDR4 memory interface (64-bit data and 8-bit ECC data), assigned in FPGA 2L, 2M, and 2N I/O banks, is connected to a 4 GB HILO x72 memory daughter card. The target design speed is 1333 MHz DDR4 bus.

Note: DDR4 HiLo daughter card is not included with H-Tile version of this development kit (DK-SOC-1SSX-H-D) and will be sold separately when available. Contact Altera if you have an urgent need for a card.
Table 46.  HPS HILO DDR4 Memory Map
Pin Name Schematic Signal Name Description
PIN_E27 MEM_DMA0 DDR4 DM
PIN_D26 MEM_DQA6 DDR4 DQ
PIN_G27 MEM_DQA0 DDR4 DQ
PIN_F27 MEM_DQA3 DDR4 DQ
PIN_C27 MEM_DQA1 DDR4 DQ
PIN_B27 MEM_DQA2 DDR4 DQ
PIN_F26 MEM_DQSA_N0 DDR4 DQSN
PIN_E26 MEM_DQSA_P0 DDR4 DQSP
PIN_B25 MEM_DQA5 DDR4 DQ
PIN_C26 MEM_DQA4 DDR4 DQ
PIN_D25 MEM_DQA7 DDR4 DQ
PIN_L26 MEM_DMA3 DDR4 DM
PIN_K27 MEM_DQA29 DDR4 DQ
PIN_M27 MEM_DQA24 DDR4 DQ
PIN_L27 MEM_DQA25 DDR4 DQ
PIN_H27 MEM_DQA28 DDR4 DQ
PIN_H26 MEM_DQA30 DDR4 DQ
PIN_K26 MEM_DQSA_N3 DDR4 DQSN
PIN_J26 MEM_DQSA_P3 DDR4 DQSP
PIN_G25 MEM_DQA26 DDR4 DQ
PIN_F25 MEM_DQA31 DDR4 DQ
PIN_H25 MEM_DQA27 DDR4 DQ
PIN_V30 MEM_DMA1 DDR4 DM
PIN_U30 MEM_DQA8 DDR4 DQ
PIN_T30 MEM_DQA9 DDR4 DQ
PIN_T29 MEM_DQA10 DDR4 DQ
PIN_U28 MEM_DQA11 DDR4 DQ
PIN_U29 MEM_DQA15 DDR4 DQ
PIN_V27 MEM_DQSA_N1 DDR4 DQSN
PIN_V28 MEM_DQSA_P1 DDR4 DQSP
PIN_V26 MEM_DQA14 DDR4 DQ
PIN_V25 MEM_DQA12 DDR4 DQ
PIN_U27 MEM_DQA13 DDR4 DQ
PIN_N25 MEM_DMA2 DDR4 DM
PIN_P25 MEM_DQA18 DDR4 DQ
PIN_P26 MEM_DQA22 DDR4 DQ
PIN_R26 MEM_DQA21 DDR4 DQ
PIN_T25 MEM_DQA17 DDR4 DQ
PIN_U25 MEM_DQA16 DDR4 DQ
PIN_R27 MEM_DQSA_N2 DDR4 DQSN
PIN_T26 MEM_DQSA_P2 DDR4 DQSP
PIN_M25 MEM_DQA23 DDR4 DQ
PIN_L25 MEM_DQA20 DDR4 DQ
PIN_N27 MEM_DQA19 DDR4 DQ
PIN_U34 MEM_DQ_ADDR_CMD0 DDR4 DM
PIN_U33 MEM_DQ_ADDR_CMD3 DDR4 DQ
PIN_T31 MEM_DQ_ADDR_CMD4 DDR4 DQ
PIN_R31 MEM_DQ_ADDR_CMD2 DDR4 DQ
PIN_T34 MEM_DQ_ADDR_CMD1 DDR4 DQ
PIN_R34 MEM_DQ_ADDR_CMD5 DDR4 DQ
PIN_T32 MEM_DQS_ADDR_CMD_N DDR4 DQSN
PIN_R32 MEM_DQS_ADDR_CMD_P DDR4 DQSP
PIN_U32 MEM_DQ_ADDR_CMD6 DDR4 DQ
PIN_V32 MEM_DQ_ADDR_CMD7 DDR4 DQ
PIN_P33 MEM_DQ_ADDR_CMD8 DDR4 DQ
PIN_R36 MEM_ADDR_CMD18 DDR4 BG0
PIN_T35 MEM_ADDR_CMD17 DDR4 BA1
PIN_L36 MEM_ADDR_CMD16 DDR4 BA0
PIN_L35 MEM_ADDR_CMD19 DDR4 A17
PIN_P36 MEM_ADDR_CMD26 DDR4 A16
PIN_N36 MEM_ADDR_CMD15 DDR4 A15
PIN_K37 MEM_ADDR_CMD14 DDR4 A14
PIN_K36 MEM_ADDR_CMD13 DDR4 A13
PIN_P35 MEM_ADDR_CMD12 DDR4 A12
PIN_N35 CLK_EMI_N EMIF Ref clockN
PIN_M35 CLK_EMI_P EMIF Ref clockP
PIN_P38 MEM_ADDR_CMD11 DDR4 A11
PIN_N37 MEM_ADDR_CMD10 DDR4 A10
PIN_R37 MEM_ADDR_CMD9 DDR4 A9
PIN_P37 MEM_ADDR_CMD8 DDR4 A8
PIN_L39 MEM_ADDR_CMD7 DDR4 A7
PIN_K39 MEM_ADDR_CMD6 DDR4 A6
PIN_J38 MEM_ADDR_CMD5 DDR4 A5
PIN_J39 MEM_ADDR_CMD4 DDR4 A4
PIN_M38 MEM_ADDR_CMD3 DDR4 A3
PIN_M37 MEM_ADDR_CMD2 DDR4 A2
PIN_L37 MEM_ADDR_CMD1 DDR4 A1
PIN_K38 MEM_ADDR_CMD0 DDR4 A0
PIN_H40 MEM_ADDR_CMD31 DDR4 PAR
PIN_J40 MEM_ADDR_CMD30 DDR4 CSN1 (not use)
PIN_G39 MEM_CLK_N DDR4 BANK CLKN
PIN_F39 MEM_CLK_P DDR4 BANK CLKP
PIN_K40 MEM_ADDR_CMD21 DDR4 CKe1 ( no use)
PIN_L40 MEM_ADDR_CMD20 DDR4 CKe0
PIN_F40 MEM_ADDR_CMD25 DDR4 ODT1 (no use)
PIN_G40 MEM_ADDR_CMD24 DDR4 ODT0
PIN_H38 MEM_ADDR_CMD23 DDR4 ACTn
PIN_G38 MEM_ADDR_CMD22 DDR4 CSn0
PIN_E40 MEM_ADDR_CMD27 DDR4 Resetn
PIN_D40 MEM_ADDR_CMD28 DDR4 BG1
PIN_J34 MEM_DMB0 DDR4 DM
PIN_K34 MEM_DQB1 DDR4 DQ
PIN_N32 MEM_DQB3 DDR4 DQ
PIN_N31 MEM_DQB6 DDR4 DQ
PIN_K33 MEM_DQB0 DDR4 DQ
PIN_K32 MEM_DQB4 DDR4 DQ
PIN_L31 MEM_DQSB_N0 DDR4 DQSN
PIN_L32 MEM_DQSB_P0 DDR4 DQSP
PIN_N33 MEM_DQB5 DDR4 DQ
PIN_M33 MEM_DQB2 DDR4 DQ
PIN_M34 MEM_DQB7 DDR4 DQ
PIN_F34 MEM_DMB2 DDR4 DM
PIN_E34 MEM_DQB17 DDR4 DQ
PIN_J35 MEM_DQB21 DDR4 DQ
PIN_H35 MEM_DQB22 DDR4 DQ
PIN_F35 MEM_DQB18 DDR4 DQ
PIN_G35 MEM_DQB20 DDR4 DQ
PIN_G34 MEM_DQSB_N2 DDR4 DQSN
PIN_G33 MEM_DQSB_P2 DDR4 DQSP
PIN_H36 MEM_DQB23 DDR4 DQ
PIN_J36 MEM_DQB19 DDR4 DQ
PIN_H33 MEM_DQB16 DDR4 DQ
PIN_D39 MEM_DMB1 DDR4 DM
PIN_E39 MEM_DQB9 DDR4 DQ
PIN_E38 MEM_DQB11 DDR4 DQ
PIN_D38 MEM_DQB12 DDR4 DQ
PIN_D35 MEM_DQB14 DDR4 DQ
PIN_D34 MEM_DQB13 DDR4 DQ
PIN_F36 MEM_DQSB_N1 DDR4 DQSN
PIN_E36 MEM_DQSB_P1 DDR4 DQSP
PIN_F37 MEM_DQB10 DDR4 DQ
PIN_E37 MEM_DQB15 DDR4 DQ
PIN_H37 MEM_DQB8 DDR4 DQ
PIN_C36 MEM_DMB3 DDR4 DM
PIN_D36 MEM_DQB26 DDR4 DQ
PIN_C35 MEM_DQB29 DDR4 DQ
PIN_B35 MEM_DQB25 DDR4 DQ
PIN_B37 MEM_DQB27 DDR4 DQ
PIN_C37 MEM_DQB31 DDR4 DQ
PIN_A35 MEM_DQSB_N3 DDR4 DQSN
PIN_A36 MEM_DQSB_P3 DDR4 DQSP
PIN_B38 MEM_DQB28 DDR4 DQ
PIN_C38 MEM_DQB30 DDR4 DQ
PIN_A37 MEM_DQB24 DDR4 DQ
PIN_A38 HPS_ALERT_N2 DDR4 Altertn
Level Two Title