Stratix® 10 SX SoC Development Kit User Guide

ID 683303
Date 6/06/2024
Public
Document Table of Contents

4.7. Connectors and Interfaces

The FPGA portion of this development kit includes 96 transceivers.

Table 12.  Channel Assignment for Transceiver Applications
Applications Channel (Bank, Number)
FMC+ A 1C (1C, 0-5), 1D (1D, 0-5), 1E (1E, 0-3), 1F (PCIE EP x16)
SFP+ Port (4C, 0)
PCIE RC x16 (4K, 0-5), (4L, 0-5), (4M, 0-3)
SGMII Port 1 and Port 2 (4M, 4), (4M, 5)
FMC+ B 1K (1K, 0-5), 1L (1L, 0-5), 1M (1M, 0-3), 1N (PCIE EPx16)
MXP Test Ports (4D, 0, 1, 3, 4)
SDI Port TX (4E,1), RX (4F, 0)
HDMI (4C, 2-5)
ZQSFP+ B (4F, (0,1,3,4))
ZQSFP+ A (4N, (0,1,3,4))