Mailbox Client Intel® FPGA IPs User Guide

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ID 683290
Date 11/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. Mailbox Client Intel FPGA IP User Guide 2. Appendix: CONFIG_STATUS and RSU_STATUS Error Code Descriptions
1. Mailbox Client Intel FPGA IP User Guide x
1.1. Release Information 1.2. Device Family Support 1.3. Parameters 1.4. Mailbox Client Intel® FPGA IP Core Interface Signals 1.5. Mailbox Client Intel FPGA IP Avalon® Memory-Mapped Interface 1.6. Commands and Responses 1.7. Specifying the Command and Response FIFO Depths 1.8. Enabling Cryptographic Services 1.9. Using the Mailbox Client Intel® FPGA IP 1.10. Accessing Quad SPI Flash Mailbox Client Intel FPGA IP Core Use Case Examples 1.11. Nios® II and Nios® V Processors HAL Driver 1.12. Mailbox Client Intel FPGA IP User Guide Archives 1.13. Document Revision History for the Mailbox Client Intel® FPGA IP User Guide
1.4. Mailbox Client Intel® FPGA IP Core Interface Signals x
1.4.1. Clock and Reset Interfaces 1.4.2. Avalon® Memory-Mapped Interface 1.4.3. AXI Manager Interface
1.5. Mailbox Client Intel FPGA IP Avalon® Memory-Mapped Interface x
1.5.1. Interrupt Enable Register 1.5.2. Interrupt Status Register 1.5.3. Timer Registers
1.6. Commands and Responses x
1.6.1. Operation Commands 1.6.2. Error Code Responses 1.6.3. Error Code Recovery
1.11. Nios® II and Nios® V Processors HAL Driver x
1.11.1. Mailbox Client HAL API 1.11.2. LibRSU HAL API
1.11.1. Mailbox Client HAL API x
1.11.1.1. Mailbox Client Driver API
1.11.2. LibRSU HAL API x
1.11.2.1. Configuration Parameter 1.11.2.2. Error Codes 1.11.2.3. Using LibRSU HAL API without Valid SPT or CPB 1.11.2.4. Data Type 1.11.2.5. Functions 1.11.2.6. RSU Client API
1. Mailbox Client Intel FPGA IP User Guide
2. Appendix: CONFIG_STATUS and RSU_STATUS Error Code Descriptions

1.5.2. Interrupt Status Register

Use the iteupt_status egiste to moito the status of the FIFO ad idetify ivalid commads.

You logic ca poll the eo bits of the iteupt_status egiste. O, you ca cofigue the EN_COMMAND_INVALID bit of the iteupt eable egiste to iteupt whe a eo occus.

Whe a eo occus, the Mailbox Cliet Itel® FPGA IP cleas all pedig esposes. You logic should ot expect ay espose fom Mailbox Cliet Itel® FPGA IP afte a eo occus. You logic must asset eset fo a miimum of 10 clock cycles to eset the Mailbox Cliet Itel® FPGA IP.

Table 9.  Iteupt Status Registe
Bit Fields Access Default Value Desciptio
31:8 Reseved
9 RD_RSP_FIFO_WHEN_EMPTY R 0x0 Read espose FIFO whe empty detectio iteupt.
  • 1: Idicates the Mailbox Cliet Itel® FPGA IP detected that you attempted a eoeous behavio to ead the espose FIFO whe it is empty which is ot allowed. You must eset the Mailbox Cliet Itel® FPGA IP.
  • 0: Idicates o eoeous behavio to ead the espose FIFO whe it is empty was detected.
8 WR_CMD_FIFO_WHEN_FULL R 0x0 Wite commad FIFO whe full detectio iteupt.
  • 1: Idicates the Mailbox Cliet Itel® FPGA IP detected that you attempted a eoeous behavio to wite to the commad FIFO whe it is full which is ot allowed. You must eset the Mailbox Cliet Itel® FPGA IP.
  • 0: Idicates o eoeous behavio to wite the commad FIFO whe it is full was detected.
7 CRYPTO_ERROR_RECOVERY_PROGRESS 8 R 0x0 Eo ecovey flow pogess iteupt fo the cyptogaphic (cypto) flow.
  • 1: Idicates that the cypto eo ecovey is i pogess. You may use this bit to epot the pogess of the soft IP eo ecovey. While i ecovey, the SDM is uable to pefom ead/wite opeatios fom the memoy.
  • 0: Idicates the cypto eo ecovey is completed.
6 CRYPTO_MEMORY_TIMEOUT 8 R 0x0 Cyptogaphic sevices time fo memoy taget iteupt. Timeout value is set by Cypto Memoy Timeout Value paamete i the Mailbox Cliet Itel® FPGA IP.
  • 1: Idicates that the timeout occued i eithe the memoy taget wite o ead path i the AXI tasactio. You must eset the Mailbox Cliet IP (i_eset ad axi_i_eset) ad you memoy taget device.
  • 0: No timeout occued
5 BACKPRESSURE_TIMEOUT R 0x0 SDM backpessue time iteupt.
  • 1: The SDM backpessue time has timeout. Idicates that a fatal eo occued i SDM. You must eset the device. To eset, ecofigue o powe cycle the device.
  • 0: The SDM backpessue time has ot timeout.
4 EOP_TIMEOUT R 0x0
Ed of Packet (EOP) time iteupt.
  • 1: Idicates that the EOP time has timeout. You must eset the Mailbox Cliet Itel® FPGA IP.
  • 0: The EOP time has ot timeout.
Idicates that the Mailbox Cliet Itel® FPGA IP did ot eceive the full commad with EOP due to:
  • Mailbox did ot eceive the last agumet with EOP.
  • Mailbox aleady eceived all agumets without the EOP i it.
3 COMMAND_INVALID R 0x0 Ivalid commad iteupt. Idicates a mismatch betwee the commad legth specified i the commad heade ad the umbe of wods set. Hadwae cleas this bit.
  • 1: Idicates that the commad is ivalid. You must eset the Mailbox Cliet Itel® FPGA IP.
  • 0: The commad is valid.
2 Reseved — — Reseved.
1 CMD_FIFO_NOT_FULL R 0x0 Commad FIFO is ot full iteupt.
  • 1: Idicates commad FIFO is ot full. The cliet ca dive data.
  • 0: Idicates the FIFO is full.

The FIFO automatically cleas this bit. You do ot eed to clea this bit maually.
0 DATA_VALID R 0x0 Data valid iteupt.
  • 1: Idicates that valid data is available. The maste ca ead.
  • 0: Idicates the FIFO is empty.

The FIFO automatically cleas this bit. You do ot eed to clea this bit maually.
8 The cypto sevice featue is oly available fo Agilex™ 7 ad Agilex™ 5 devices.
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