Mailbox Client Intel® FPGA IPs User Guide

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ID 683290
Date 11/04/2024
Public
Document Table of Contents
Document Table of Contents x
1. Mailbox Client Intel FPGA IP User Guide 2. Appendix: CONFIG_STATUS and RSU_STATUS Error Code Descriptions
1. Mailbox Client Intel FPGA IP User Guide x
1.1. Release Information 1.2. Device Family Support 1.3. Parameters 1.4. Mailbox Client Intel® FPGA IP Core Interface Signals 1.5. Mailbox Client Intel FPGA IP Avalon® Memory-Mapped Interface 1.6. Commands and Responses 1.7. Specifying the Command and Response FIFO Depths 1.8. Enabling Cryptographic Services 1.9. Using the Mailbox Client Intel® FPGA IP 1.10. Accessing Quad SPI Flash Mailbox Client Intel FPGA IP Core Use Case Examples 1.11. Nios® II and Nios® V Processors HAL Driver 1.12. Mailbox Client Intel FPGA IP User Guide Archives 1.13. Document Revision History for the Mailbox Client Intel® FPGA IP User Guide
1.4. Mailbox Client Intel® FPGA IP Core Interface Signals x
1.4.1. Clock and Reset Interfaces 1.4.2. Avalon® Memory-Mapped Interface 1.4.3. AXI Manager Interface
1.5. Mailbox Client Intel FPGA IP Avalon® Memory-Mapped Interface x
1.5.1. Interrupt Enable Register 1.5.2. Interrupt Status Register 1.5.3. Timer Registers
1.6. Commands and Responses x
1.6.1. Operation Commands 1.6.2. Error Code Responses 1.6.3. Error Code Recovery
1.11. Nios® II and Nios® V Processors HAL Driver x
1.11.1. Mailbox Client HAL API 1.11.2. LibRSU HAL API
1.11.1. Mailbox Client HAL API x
1.11.1.1. Mailbox Client Driver API
1.11.2. LibRSU HAL API x
1.11.2.1. Configuration Parameter 1.11.2.2. Error Codes 1.11.2.3. Using LibRSU HAL API without Valid SPT or CPB 1.11.2.4. Data Type 1.11.2.5. Functions 1.11.2.6. RSU Client API
1. Mailbox Client Intel FPGA IP User Guide
2. Appendix: CONFIG_STATUS and RSU_STATUS Error Code Descriptions

1.5.1. Interrupt Enable Register

Use the Iteupt Eable egiste to eable o disable iteupts.
Note: These eable bits do ot pevet the value of iteupt status bit fom showig up i ISR, they oly pevet the iteupt status bit fom causig iteupt output assetio via IRQ sigal.
Table 8.  Iteupt Eable Registe
Bit Fields Access Default Value Desciptio
31:8 Reseved
9 EN_RD_RSP_FIFO_WHEN_EMPTY R/W 0x0 The eable iteupt bit fo ead espose FIFO whe empty detectio.
  • 1: Eable the ead espose FIFO whe empty detectio iteupt bit.
  • 0: Disable the ead espose FIFO whe empty detectio iteupt bit.
8 EN_WR_CMD_FIFO_WHEN_FULL R/W 0x0 The eable iteupt bit fo wite commad FIFO whe full detectio.
  • 1: Eable the wite commad FIFO whe full iteupt bit
  • 0: Disable the wite commad FIFO whe full iteupt bit
7 EN_CRYPTO_ERROR_RECOVERY_PROGRESS 7 R/W 0x0 The eable iteupt bit fo cypto sevice eo ecovey pogess status.
  • 1: Eable the cypto sevice eo ecovey pogess iteupt
  • 0: Disable the cypto sevice eo ecovey pogess iteupt
6 EN_CRYPTO_MEMORY_TIMEOUT 7 R/W 0x0 The eable iteupt bit fo the cypto sevice cliet-side memoy timeout.
  • 1: Eable the cypto sevice cliet-side memoy timeout iteupt
  • 0: Disable the cypto sevice cliet-side memoy timeout iteupt
5 EN_BACKPRESSURE_TIMEOUT R/W 0x0 The eable iteupt bit fo SDM backpessue timeout.
  • 1: Eable the SDM backpessue timeout iteupt
  • 0: Disable the SDM backpessue timeout iteupt
4 EN_EOP_TIMEOUT R/W 0x0 The eable iteupt bit fo EN_EOP_TIMEOUT.
  • 1: Eable the EOP timeout iteupt
  • 0: disable the EOP timeout iteupt
3 EN_COMMAND_INVALID R/W 0x0 The eable iteupt bit fo COMMAND_INVALID.
  • 1: Eable the commad ivalid iteupt
  • 0: Disable the commad ivalid iteupt
2 Reseved — — Reseved.
1 EN_CMD_FIFO_NOT_FULL R/W 0x0 The eable fo the commad FIFO full iteupt.
  • 1: Eable the FIFO full iteupt
  • 0: Disable the FIFO full iteupt
0 EN_DATA_VALID R/W 0x0 The eable fo the data valid iteupt.
  • 1: Eable the data valid iteupt
  • 0: Disable the data valid iteupt
7 The cypto sevice featue is oly available fo Agilex™ 7 ad Agilex™ 5 devices.
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