Clocking and PLL User Guide: Agilex™ 5 FPGAs and SoCs

ID 813671
Date 7/25/2024
Public
Document Table of Contents

6.4. Reconfiguration Guideline for I/O PLLs

Note: The PLL may lose lock and cause reliability problems for your device if you configure it with the wrong PLL setting, configure the wrong bit, or overwrite the whole byte for settings that make up just part of one byte.