Clocking and PLL User Guide: Agilex™ 5 FPGAs and SoCs

ID 813671
Date 7/25/2024
Public
Document Table of Contents

6.6.2. Data Bus Setting for Clock Gating Reconfiguration

Table 20.  Output Clock and The Corresponding Data Bit Setting For Clock Gating
Reconfiguration Mode Write Address Bus Setting [7:0] Output Clock Data Bit Setting
Clock Gating 0x54 C0 data [18]

Gated = 1'b0

Ungated = 1'b1

C1 data [19]
C2 data [20]
C3 data [21]
C4 data [22]
C5 data [23]
C6 data [24]