Visible to Intel only — GUID: ccy1673422000087
Ixiasoft
Visible to Intel only — GUID: ccy1673422000087
Ixiasoft
2.1.3.1.4. LAB Clock Gate
The Agilex™ 5 LAB register has built-in clock gating functionality. The register clock enable mechanism is a hardened data feedback, as shown in the Clock Gating and Clock Divider in Agilex™ 5 Clock Network diagram. The LAB clock gate offers no associated power savings because this is a purely functional clock enable.
The Quartus® Prime Analysis & Synthesis stage of the Compiler infers a LAB clock gate from a behavioral description of clock gating in the register transfer level (RTL). If you want a physical clock gate, you must instantiate it explicitly.