Clocking and PLL User Guide: Agilex™ 5 FPGAs and SoCs

ID 813671
Date 7/25/2024
Public
Document Table of Contents

2.2.6.3. Source Synchronous Compensation Mode

If the data and clock signals arrive at the same time on the input pins, the same phase relationship is maintained at the clock and data ports of any IOE input register. Data and clock signals at the IOE experience similar buffer delays if you use the same I/O standard. Only one output clock can be compensated in source synchronous compensation mode.

Altera recommends source synchronous mode for source synchronous data transfers.

Figure 14. Example of Phase Relationship Between Clock and Data in Source Synchronous Mode


The source synchronous mode compensates for the delay of the clock network used and any difference in the delay between the following two paths:

  • Data pin to the IOE register input
  • Clock input pin to the PLL PFD input

The Agilex™ 5 PLL can compensate multiple pad-to-input-register paths, such as a data bus when it is set to use source synchronous compensation mode. The fabric-feeding PLL located within HVIO bank 6E, 6F/6G, and 6H does not support the compensation mode.