Clocking and PLL User Guide: Agilex™ 5 FPGAs and SoCs

ID 813671
Date 7/25/2024
Public
Document Table of Contents

2.1.1. Clock Network Architecture

Each Agilex™ 5 device is divided into a number of evenly sized clock sectors.

Clock Sector in an Agilex™ 5 devices is implemented as an array of sectors. The following figure shows the clock sector example of 5 rows, and 6 columns. I/O banks are at the top and bottom of the Agilex™ 5 devices.
Figure 1. Clock Sector Floorplan for Agilex™ 5 Devices