Clocking and PLL User Guide: Agilex™ 5 FPGAs and SoCs

ID 813671
Date 7/25/2024
Public
Document Table of Contents

6.4.1. Enabling Reconfiguration for The Desired I/O PLL

  1. Set the address bus value for according to the table below:
    Address Bus Value for HSIO I/O PLL Reconfiguration Address Bus Value for HVIO I/O PLL Reconfiguration Value
    s0_axi4lite_awaddr [7:0] core_avl_address [8:0] 0x10
    s0_axi4lite_awaddr [20:13] - I/O PLL Base Address
    s0_axi4lite_awaddr [23:21] - 3’b101
  2. Set the LSB of data bus value to 1’b1 to enable read and write operation.