Clocking and PLL User Guide: Agilex™ 5 FPGAs and SoCs

ID 813671
Date 7/25/2024
Public
Document Table of Contents

6.4.3. Reconfiguring The I/O PLL

  1. Set the address bus value according to the table below:
    Table 16.  Reconfiguring The I/O PLL
    Address Bus Value for HSIO I/O PLL Reconfiguration Address Value for HVIO I/O PLL Reconfiguration Value
    s0_axi4lite_awaddr [7:0]

    core_avl_address [8:0]

    Divide Settings Address
    s0_axi4lite_awaddr [20:13] I/O PLL Base Address
    s0_axi4lite_awaddr [23:21] 3’b101
  2. Set the address bus value for s0_axi4lite_awaddr [7:0]/core_avl_address [8:0] and the data bus value for [31:0] as the desired PLL setting. For more details about the Reconfiguration tables, refer to Address Bus and Data Bus Settings.
  3. Repeat the steps above to set the address bus and data bus value for the desired I/O PLL reconfiguration setting.
  4. Set address bus value of s0_axi4lite_awaddr [7:0]/core_avl_address [8:0] = 0x80 and assert data bus value for [2] for 10 ns to reset PLL.
  5. After the I/O PLL reconfiguration is complete, you must manually trigger the I/O PLL recalibration.