Clocking and PLL User Guide: Agilex™ 5 FPGAs and SoCs

ID 813671
Date 7/25/2024
Public
Document Table of Contents

5. IOPLL Intel® FPGA IP Core

The IOPLL Intel® FPGA IP core allows you to configure the settings of the Agilex™ 5 I/O PLL.

The IOPLL IP core supports the following features:

  • Supports six different clock feedback modes: direct, external feedback, normal, source synchronous, zero delay buffer, and LVDS mode.
  • Generates up to four output clocks for I/O bank I/O PLL and seven output clocks for fabric-feeding I/O PLL for the Agilex™ 5 device.
  • Switches between two reference input clocks.
  • Supports adjacent PLL (adjpllin) input to connect with an upstream PLL in PLL dedicated cascading mode.

The IOPLL IP core is available under the Basic Functions > PLL category of the IP Catalog.