Clocking and PLL User Guide: Agilex™ 5 FPGAs and SoCs

ID 813671
Date 7/25/2024
Public
Document Table of Contents

6.4.2. Clearing off Calibration Statuses

  1. Set the address bus value for s0_axi4lite_awaddr according to the table below:
    Table 15.  Clearing off Calibration Statuses
    Address Bus Value for HSIO I/O PLL Reconfiguration Address Value for HVIO I/O PLL Reconfiguration Value
    s0_axi4lite_awaddr [7:0] core_avl_address [8:0] Calibration Addresses
    s0_axi4lite_awaddr [20:13] I/O PLL Base Address
    s0_axi4lite_awaddr [23:21] 3’b101
  2. For address bus value of s0_axi4lite_awaddr [7:0]/core_avl_address[8:0] = 0x54, set the data bus value of bit [31] to 1’b0
  3. For address bus value s0_axi4lite_awaddr [7:0]/core_avl_address[8:0] = 0x58, set the data bus value of bit [7] and bit [21] to 1’b0
  4. For address bus value of s0_axi4lite_awaddr [7:0]/core_avl_address [8:0]= 0x84, set the data bus value for bit [0] and bit [8] to 1’b0