Clocking and PLL User Guide: Agilex™ 5 FPGAs and SoCs

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ID 813671
Date 7/25/2024
Public
Document Table of Contents
Document Table of Contents x
1. Agilex™ 5 Clocking and PLL Overview 2. Agilex™ 5 Clocking and PLL Architecture and Features 3. Agilex™ 5 Clocking and PLL Design Considerations 4. Clock Control Intel® FPGA IP Core 5. IOPLL Intel® FPGA IP Core 6. I/O PLL Reconfiguration 7. Document Revision History for the Clocking and PLL User Guide: Agilex™ 5 FPGAs and SoCs
1. Agilex™ 5 Clocking and PLL Overview x
1.1. Clock Networks Overview 1.2. PLLs Overview
2. Agilex™ 5 Clocking and PLL Architecture and Features x
2.1. Clock Networks Architecture and Features 2.2. PLLs Architecture and Features
2.1. Clock Networks Architecture and Features x
2.1.1. Clock Network Architecture 2.1.2. Clock Resources 2.1.3. Clock Control Features
2.1.1. Clock Network Architecture x
2.1.1.1. Clock Network Hierarchy 2.1.1.2. Clock Sectors 2.1.1.3. Programmable Clock Routing
2.1.3. Clock Control Features x
2.1.3.1. Clock Gating 2.1.3.2. Clock Divider
2.1.3.1. Clock Gating x
2.1.3.1.1. Root Clock Gate 2.1.3.1.2. Sector Clock Gate 2.1.3.1.3. I/O PLL Clock Gate 2.1.3.1.4. LAB Clock Gate
2.2. PLLs Architecture and Features x
2.2.1. PLL Features 2.2.2. PLL Usage 2.2.3. PLL Locations 2.2.4. PLL Architecture 2.2.5. PLL Control Signals 2.2.6. PLL Feedback Modes 2.2.7. Clock Multiplication and Division 2.2.8. Programmable Phase Shift 2.2.9. Programmable Duty Cycle 2.2.10. PLL Cascading 2.2.11. PLL Input Clock Switchover 2.2.12. PLL Reconfiguration and Dynamic Phase Shift 2.2.13. PLL Calibration
2.2.5. PLL Control Signals x
2.2.5.1. Reset 2.2.5.2. Locked
2.2.6. PLL Feedback Modes x
2.2.6.1. Direct Compensation Mode 2.2.6.2. LVDS Compensation Mode 2.2.6.3. Source Synchronous Compensation Mode 2.2.6.4. Normal Compensation Mode 2.2.6.5. Zero-Delay Buffer Mode 2.2.6.6. External Feedback Mode
2.2.11. PLL Input Clock Switchover x
2.2.11.1. Automatic Switchover 2.2.11.2. Automatic Switchover with Manual Override 2.2.11.3. Manual Clock Switchover
2.2.13. PLL Calibration x
2.2.13.1. Power-Up Calibration 2.2.13.2. User Calibration 2.2.13.3. Static Phase Error Calibration
3. Agilex™ 5 Clocking and PLL Design Considerations x
3.1. Guidelines: Clock Switchover 3.2. Guidelines: Timing Closure 3.3. Guidelines: Resetting the PLL 3.4. Guidelines: Configuration Constraints 3.5. Clocking Constraints 3.6. IP Core Constraints 3.7. Guideline: Achieving 5% Duty Cycle for fOUT_EXT ≥ 300 MHz Using tx_outclk Port from LVDS SERDES Intel® FPGA IP
4. Clock Control Intel® FPGA IP Core x
4.1. Release Information for Clock Control Intel® FPGA IP 4.2. Clock Control IP Core Parameters 4.3. Clock Control IP Core Ports and Signals
5. IOPLL Intel® FPGA IP Core x
5.1. Release Information for IOPLL Intel® FPGA IP Core 5.2. IOPLL IP Core Parameters 5.3. IOPLL IP Core Ports and Signals
5.2. IOPLL IP Core Parameters x
5.2.1. IOPLL IP Core Parameters - PLL Tab 5.2.2. IOPLL IP Core Parameters - Settings Tab 5.2.3. IOPLL IP Core Parameters - Cascading Tab 5.2.4. IOPLL IP Core Parameters - Advanced Parameters Tab
6. I/O PLL Reconfiguration x
6.1. Release Information for EMIF Calibration IP 6.2. Implementing HSIO I/O PLL Reconfiguration using EMIF Calibration IP 6.3. Implementing HVIO I/O PLL Reconfiguration 6.4. Reconfiguration Guideline for I/O PLLs 6.5. Axilite Interface Ports in the EMIF Calibration IP 6.6. Address Bus and Data Bus Settings
6.2. Implementing HSIO I/O PLL Reconfiguration using EMIF Calibration IP x
6.2.1. Setting Up the IOPLL Intel® FPGA IP 6.2.2. Setting Up the EMIF Calibration IP 6.2.3. Connectivity Between IOPLL and EMIF Calibration IP
6.3. Implementing HVIO I/O PLL Reconfiguration x
6.3.1. Setting Up the IOPLL Intel® FPGA IP 6.3.2. Read and Write Operations
6.4. Reconfiguration Guideline for I/O PLLs x
6.4.1. Enabling Reconfiguration for The Desired I/O PLL 6.4.2. Clearing off Calibration Statuses 6.4.3. Reconfiguring The I/O PLL 6.4.4. Recalibration of I/O PLL 6.4.5. Clock Gating (Optional)
6.6. Address Bus and Data Bus Settings x
6.6.1. Divide Settings and the Corresponding Data Bit Setting for Reconfiguration 6.6.2. Data Bus Setting for Clock Gating Reconfiguration 6.6.3. Data Bus Setting For Charge Pump Current
1. Agilex™ 5 Clocking and PLL Overview
2. Agilex™ 5 Clocking and PLL Architecture and Features
3. Agilex™ 5 Clocking and PLL Design Considerations
4. Clock Control Intel® FPGA IP Core
5. IOPLL Intel® FPGA IP Core
6. I/O PLL Reconfiguration
7. Document Revision History for the Clocking and PLL User Guide: Agilex™ 5 FPGAs and SoCs

2.2.1. PLL Features

Table 2.  PLL Features in Agilex™ 5 Devices—Preliminary
Feature I/O Bank I/O PLL 3 Fabric-Feeding I/O PLL3
Integer PLL Yes Yes
Number of C output counter 4 7 or 24
M counter divide factor range 4 to 320 4 to 320
N counter divide factor range 1 to 110 1 to 110
C counter divide factor range 1 to 510 1 to 510
Dedicated external clock outputs 5 Yes —
Dedicated clock input pins6 7 Yes Yes
External feedback input pin Yes —
Source synchronous compensation 8 Yes Yes
Direct compensation Yes Yes
Normal compensation 9 Yes Yes
Zero-delay buffer compensation Yes —
External feedback compensation Yes —
LVDS compensation Yes —
Voltage-controlled oscillator (VCO) output drives the DPA clock Yes —
Phase shift resolution 10 39.0625 ps 39.0625 ps
Programmable duty cycle Yes Yes
Power down mode Yes Yes
Bandwidth setting11 — —
Spread-spectrum input clock tracking 12 Yes Yes
Table 3.  Spread-Spectrum Input Clocking Supported Profile
Spread-Spectrum Clocking Parameter Setting
Modulation frequency 200 kHz
Center or down spread Down spread
Frequency deviation ±1%
Modulation profile Triangle
3 I/O PLL Type is determined by the Quartus® Prime software automatically, based on the assigned location of the I/O PLL in Assignment Editor.
4 The fabric-feeding PLLs located within HVIO bank 6E, 6F, 6G ,6H only feature two output counters.
5 For dedicated external clock outputs, you must enable access to external clock output port through IOPLL Intel® FPGA IP core. There are 2 dedicated external clock output available for each I/O bank I/O PLL. I/O PLL only supports True Differential Signaling I/O Standard for dedicated external clock outputs.
6 I/O PLL only supports True Differential Signaling I/O Standard for dedicated clock input pins.
7 The PLL's dedicated refclk pin supports different IO standards depending on where the PLL was placed. While you use the HVIO, ensure to set the I/O Standard of the pin to HVIO I/O Standard.
8 Non-dedicated feedback path option is available for this compensation mode. The fabric-feeding PLL located within HVIO bank 6E, 6F/6G, and 6H does not support the compensation mode.
9 Non-dedicated feedback path option is also available for normal compensation. The fabric-feeding PLL located within HVIO bank 6E, 6F/6G, and 6H does not support the compensation mode.
10 The smallest phase shift is determined by the VCO period divided by eight. For degree increments, the Agilex™ 5 device can shift all output frequencies in increments of at least 45°. Smaller degree increments are possible depending on the frequency and divide parameters.
11 Bandwidth setting is selected by the Quartus® Prime software automatically depending on the M counter value.
12 Provided that input clock jitter is within the input jitter tolerance specifications. Altera recommends that the spread-spectrum support profile is down spread, ±0.5% and Fmod = 200 kHz.
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