Clocking and PLL User Guide: Agilex™ 5 FPGAs and SoCs

ID 813671
Date 7/25/2024
Public

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Document Table of Contents

2.2.1. PLL Features

Table 2.  PLL Features in Agilex™ 5 Devices—Preliminary
Feature I/O Bank I/O PLL 3 Fabric-Feeding I/O PLL3
Integer PLL Yes Yes
Number of C output counter 4 7 or 24
M counter divide factor range 4 to 320 4 to 320
N counter divide factor range 1 to 110 1 to 110
C counter divide factor range 1 to 510 1 to 510
Dedicated external clock outputs 5 Yes
Dedicated clock input pins6 7 Yes Yes
External feedback input pin Yes
Source synchronous compensation 8 Yes Yes
Direct compensation Yes Yes
Normal compensation 9 Yes Yes
Zero-delay buffer compensation Yes
External feedback compensation Yes
LVDS compensation Yes
Voltage-controlled oscillator (VCO) output drives the DPA clock Yes
Phase shift resolution 10 39.0625 ps 39.0625 ps
Programmable duty cycle Yes Yes
Power down mode Yes Yes
Bandwidth setting11
Spread-spectrum input clock tracking 12 Yes Yes
Table 3.  Spread-Spectrum Input Clocking Supported Profile
Spread-Spectrum Clocking Parameter Setting
Modulation frequency 200 kHz
Center or down spread Down spread
Frequency deviation ±1%
Modulation profile Triangle
3 I/O PLL Type is determined by the Quartus® Prime software automatically, based on the assigned location of the I/O PLL in Assignment Editor.
4 The fabric-feeding PLLs located within HVIO bank 6E, 6F, 6G ,6H only feature two output counters.
5 For dedicated external clock outputs, you must enable access to external clock output port through IOPLL Intel® FPGA IP core. There are 2 dedicated external clock output available for each I/O bank I/O PLL. I/O PLL only supports True Differential Signaling I/O Standard for dedicated external clock outputs.
6 I/O PLL only supports True Differential Signaling I/O Standard for dedicated clock input pins.
7 The PLL's dedicated refclk pin supports different IO standards depending on where the PLL was placed. While you use the HVIO, ensure to set the I/O Standard of the pin to HVIO I/O Standard.
8 Non-dedicated feedback path option is available for this compensation mode. The fabric-feeding PLL located within HVIO bank 6E, 6F/6G, and 6H does not support the compensation mode.
9 Non-dedicated feedback path option is also available for normal compensation. The fabric-feeding PLL located within HVIO bank 6E, 6F/6G, and 6H does not support the compensation mode.
10 The smallest phase shift is determined by the VCO period divided by eight. For degree increments, the Agilex™ 5 device can shift all output frequencies in increments of at least 45°. Smaller degree increments are possible depending on the frequency and divide parameters.
11 Bandwidth setting is selected by the Quartus® Prime software automatically depending on the M counter value.
12 Provided that input clock jitter is within the input jitter tolerance specifications. Altera recommends that the spread-spectrum support profile is down spread, ±0.5% and Fmod = 200 kHz.