Clocking and PLL User Guide: Agilex™ 5 FPGAs and SoCs

ID 813671
Date 7/25/2024
Public
Document Table of Contents

5.2.3. IOPLL IP Core Parameters - Cascading Tab

Table 10.   IOPLL IP Core Parameters - Cascading Tab
Parameter Value Description
Connect to an upstream PLL through Core clock Network Cascading (create a permit_cal input signal) On or Off Turn on to create an input port to enable destination (downstream) PLL power-up calibration. Connect source (upstream) PLL locked signal to this input port.
Connect outclk to a downstream PLL through Core Clock Network Cascading On or Off Turn on to configure the PLL as an upstream PLL. Connect (upstream) PLL output clock signal to the refclk port of (downstream) PLL.
cascade_out source 56 17 Specifies which output clock to be used as cascading source.
Create an adjpllin or cclk signal to connect with an upstream PLL On or Off Turn on to create an input port, which indicates that this PLL is a destination and connects with a source (upstream) PLL.
Create a cascade_out signal to connect to a downstream PLL. On or Off Turn on to create the cascade_out port, which indicates that this PLL is a source and connects with a destination (downstream) PLL.
Enable dynamic reconfiguration of PLL On or Off Select this option to enable the dynamic reconfiguration of this IOPLL. Creates AVL interface reconfiguration port, through which current M, N, and C counter settings are read from the IOPLL, and new settings are written to the IOPLL.
Enable dynamic reconfiguration of PLL using Calibration IP On or Off Select this option to enable the dynamic reconfiguration of this IOPLL (in conjunction with EMIF Calibration IP). This option initiates calbus reconfiguration ports, which allow for the reading of the current M, N, and C counter settings from the IOPLL and the writing of new settings to the IOPLL.
17 When outclk6 is enabled, cascade_out source can only be C6; cascade_out source can be C5 only if outclk6 is not enabled.