Clocking and PLL User Guide: Agilex™ 5 FPGAs and SoCs

ID 813671
Date 7/25/2024
Public
Document Table of Contents

6.3.1. Setting Up the IOPLL Intel® FPGA IP

Figure 28. IOPLL Intel® FPGA IP
At the dynamic reconfiguration tab, enable dynamic reconfiguration of PLL.