Clocking and PLL User Guide: Agilex™ 5 FPGAs and SoCs

ID 813671
Date 7/25/2024
Public
Document Table of Contents

7. Document Revision History for the Clocking and PLL User Guide: Agilex™ 5 FPGAs and SoCs

Document Version Quartus® Prime Version Changes
2024.07.25 24.2
  • Updated the following tables:
    • IOPLL IP Core Parameters - Cascading Tab.
    • IOPLL IP Core Ports for Agilex™ 5 Devices.
  • Added footnotes in the following topics:
    • Source Synchronous Compensation Mode
    • Normal Compensation Mode
  • Added new chapter I/O PLL Reconfiguration.
2024.04.01 24.1 Initial release.