Visible to Intel only — GUID: heu1720013307437
Ixiasoft
Visible to Intel only — GUID: heu1720013307437
Ixiasoft
6. I/O PLL Reconfiguration
The Agilex™ 5 Series I/O PLL supports dynamic reconfiguration when the device is in user mode. With the dynamic reconfiguration feature, you can reconfigure the I/O PLL settings in real-time. You can change the divide settings of the PLL without the need to reconfigure the entire FPGA. The Agilex™ 5 Series I/O PLL uses divide counters (N, M, and C counters) and a voltage-controlled oscillator (VCO) to synthesize the desired phase and frequency output.
For HSIO I/O PLLs, you can reconfigure the divide settings via AXI4-Lite interfaces within the EMIF Calibration IP. For I/O PLLs in the HVIO blocks, you can directly reconfigure the divide settings by accessing the reconfiguration ports.
You can use the feature as follows:
- I/O PLL Reconfiguration
- Enable dynamic reconfiguration of PLL the dynamic reconfiguration tab of the IOPLL Intel® FPGA IP to reconfigure the individual I/O PLL registers. You can also perform dynamic phase shift.
- Recalibration of the I/O PLL
- Perform recalibration of the I/O PLL without any reconfiguration.
- Trigger recalibration if the reference clock frequency changes.
- I/O PLL clock gating
- Gate and un-gate I/O PLL output clock 0 to output clock 6 of the I/O PLL.