AN 1003: Multi Memory IP System Resource Planning: for Intel Agilex® 7 M-Series FPGAs

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ID 788295
Date 11/22/2023
Public
Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs 2. About This Application Note 3. Component Bandwidth Projections and Limitations 4. Resource Planning for Intel Agilex® 7 M-Series FPGAs 5. Factors Affecting NoC Performance 6. Debugging the NoC 7. Document Revision History of AN 1003: Multi Memory IP System Resource Planning for Intel Agilex® 7 M-Series FPGAs
2. About This Application Note x
2.1. Preliminary Guidelines 2.2. Document Prerequisites 2.3. Terminology for Intel Agilex® 7 M-Series FPGAs
3. Component Bandwidth Projections and Limitations x
3.1. Memory Controller Efficiency 3.2. Hard Memory NoC Bandwidth 3.3. Overall Bandwidth for NoC Systems
3.1. Memory Controller Efficiency x
3.1.1. HBM2E UIB Controller Efficiency 3.1.2. External Memory Interface Controller Efficiency
3.2. Hard Memory NoC Bandwidth x
3.2.1. Horizontal NoC Bandwidth 3.2.2. Initiator NoC Bandwidth 3.2.3. Target NoC Bandwidth 3.2.4. Initiator Target Link Bandwidth
4. Resource Planning for Intel Agilex® 7 M-Series FPGAs x
4.1. Hard Memory NoC Resource Planning Overview 4.2. I/O Bank Blockage 4.3. Planning Avalon® Streaming Utilization 4.4. Planning for Initiator Blockage Impact from GPIO, LVDS SERDES, and PHY Lite Bypass Mode 4.5. Planning NoC PLL and I/O PLL 4.6. Pin Planning for HPS EMIF 4.7. Planning for an External Memory Interface 4.8. Planning for HBM2E 4.9. Planning for the Fabric NoC 4.10. Planning for AXI4-Lite 4.11. Planning NoC and Memory Solution Clocks
4.2. I/O Bank Blockage x
4.2.1. Top Hard Memory NoC 4.2.2. Bottom Hard Memory NoC
4.10. Planning for AXI4-Lite x
4.10.1. Single AXI4 Lite Initiator for Each Horizontal NoC 4.10.2. AXI4-Lite Initiator for HBM2E 4.10.3. AXI4-Lite Initiator for EMIF
4.11. Planning NoC and Memory Solution Clocks x
4.11.1. Clocking without the Fabric NoC 4.11.2. Clocking with the Fabric NoC
5. Factors Affecting NoC Performance x
5.1. Recommended Performance Tuning Procedure 5.2. NoC Initiator and Target Clock Rate 5.3. Recommended NoC Design Topologies 5.4. Traffic Access Pattern and Memory Controller Efficiency 5.5. Traffic Access Pattern Due To Multiple Traffic Flows 5.6. Transaction Size 5.7. Congestion Interaction 5.8. Bandwidth Sharing At Each Switch 5.9. Exceeding NoC Bandwidth Limits 5.10. Maximum Number of Outstanding Transactions 5.11. QoS Priority 5.12. AxID 5.13. Example: 2x2 HBM Crossbars 5.14. Example: 16x16 Crossbar
5.3. Recommended NoC Design Topologies x
5.3.1. 1:1 Connectivity with EMIF and HBM 5.3.2. HBM Crossbars 5.3.3. Connectivity with HPS
6. Debugging the NoC x
6.1. Debugging NoC AXI Transaction Issues 6.2. Debugging NoC Bit Errors 6.3. Debugging NoC Performance Issues
6.3. Debugging NoC Performance Issues x
6.3.1. Measuring Performance with the Signal Tap Logic Analyzer 6.3.2. Measuring Performance with the Performance Monitor 6.3.3. Performance Debug Steps
1. Answers to Top FAQs
2. About This Application Note
3. Component Bandwidth Projections and Limitations
4. Resource Planning for Intel Agilex® 7 M-Series FPGAs
5. Factors Affecting NoC Performance
6. Debugging the NoC
7. Document Revision History of AN 1003: Multi Memory IP System Resource Planning for Intel Agilex® 7 M-Series FPGAs

6.3.3. Performance Debug Steps

To debug a performance issue, determine whether the issue is caused by controller efficiency or congestion in the NoC. Apply the appropriate improvement methods according to the steps below.
  1. Use design simulation to indicate whether memory controller efficiency is an issue. The NoC simulation model does not consider NoC congestion, but does include approximately accurate interleaving of traffic reaching the target. If the performance problem persists in simulation, this is indicative of a controller efficiency issue, or insufficiently high clock rate for the initiators or target.
  2. If possible in your system, disable traffic to all other connections, except for the NoC target of interest and all of its connected initiators. If the problem resolves, this indicates that the source of the problem is congestion from connections on the NoC. If the problem does not resolve, the likely cause is the load of other connections to that same target, or memory controller efficiency.
  3. If you suspect the performance issue is related to memory controller efficiency, review the access pattern for each initiator, and the effective access pattern when multiple initiators send transactions to one target. Consider using the following techniques to improve efficiency and performance:
    • Increase the transaction size if your application permits. Refer to Transaction Size.
    • Implement address re-ordering to suit your access pattern. The HBM2E Intel FPGA IP supports address re-ordering, which changes the mapping between your logical address and the memory physical address (row, column, bank, bank group).
    • If your application can take advantage of it, enable auto-precharge control if using the HBM2E Intel FPGA IP.
  4. If you suspect the performance issue is related to congestion, move NoC initiators and targets to reduce overlap between critical connections and other traffic, if possible. Refer to Congestion Interaction.
  5. To reduce throughput on less critical connections that overlap more critical, congested connections, modify the transaction issue rate in your design. In general, making critical connections as short as possible is also beneficial.
  6. To raise the priority of critical connections and decrease the priority of less critical connections, apply the QoS priority feature. Refer to QoS Priority.

Congestion can be caused by memory controller efficiency, as Congestion Interaction describes. A connection with a high number of outstanding transactions that is limited by the target throughput that includes controller efficiency, causes congestion of overlapping traffic. This congestion occurs because slow moving traffic queues in the NoC. For such connections, implement the following changes:

  • Move the connection to a dedicated path on the NoC that does not overlap with other traffic. A direct connection through a switch is optimal.
  • Limit the transaction issue rate in your application to reduce the number of outstanding transactions that queue in the NoC.
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