AN 1003: Multi Memory IP System Resource Planning: for Intel Agilex® 7 M-Series FPGAs

Download PDF
ID 788295
Date 11/22/2023
Public
Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs 2. About This Application Note 3. Component Bandwidth Projections and Limitations 4. Resource Planning for Intel Agilex® 7 M-Series FPGAs 5. Factors Affecting NoC Performance 6. Debugging the NoC 7. Document Revision History of AN 1003: Multi Memory IP System Resource Planning for Intel Agilex® 7 M-Series FPGAs
2. About This Application Note x
2.1. Preliminary Guidelines 2.2. Document Prerequisites 2.3. Terminology for Intel Agilex® 7 M-Series FPGAs
3. Component Bandwidth Projections and Limitations x
3.1. Memory Controller Efficiency 3.2. Hard Memory NoC Bandwidth 3.3. Overall Bandwidth for NoC Systems
3.1. Memory Controller Efficiency x
3.1.1. HBM2E UIB Controller Efficiency 3.1.2. External Memory Interface Controller Efficiency
3.2. Hard Memory NoC Bandwidth x
3.2.1. Horizontal NoC Bandwidth 3.2.2. Initiator NoC Bandwidth 3.2.3. Target NoC Bandwidth 3.2.4. Initiator Target Link Bandwidth
4. Resource Planning for Intel Agilex® 7 M-Series FPGAs x
4.1. Hard Memory NoC Resource Planning Overview 4.2. I/O Bank Blockage 4.3. Planning Avalon® Streaming Utilization 4.4. Planning for Initiator Blockage Impact from GPIO, LVDS SERDES, and PHY Lite Bypass Mode 4.5. Planning NoC PLL and I/O PLL 4.6. Pin Planning for HPS EMIF 4.7. Planning for an External Memory Interface 4.8. Planning for HBM2E 4.9. Planning for the Fabric NoC 4.10. Planning for AXI4-Lite 4.11. Planning NoC and Memory Solution Clocks
4.2. I/O Bank Blockage x
4.2.1. Top Hard Memory NoC 4.2.2. Bottom Hard Memory NoC
4.10. Planning for AXI4-Lite x
4.10.1. Single AXI4 Lite Initiator for Each Horizontal NoC 4.10.2. AXI4-Lite Initiator for HBM2E 4.10.3. AXI4-Lite Initiator for EMIF
4.11. Planning NoC and Memory Solution Clocks x
4.11.1. Clocking without the Fabric NoC 4.11.2. Clocking with the Fabric NoC
5. Factors Affecting NoC Performance x
5.1. Recommended Performance Tuning Procedure 5.2. NoC Initiator and Target Clock Rate 5.3. Recommended NoC Design Topologies 5.4. Traffic Access Pattern and Memory Controller Efficiency 5.5. Traffic Access Pattern Due To Multiple Traffic Flows 5.6. Transaction Size 5.7. Congestion Interaction 5.8. Bandwidth Sharing At Each Switch 5.9. Exceeding NoC Bandwidth Limits 5.10. Maximum Number of Outstanding Transactions 5.11. QoS Priority 5.12. AxID 5.13. Example: 2x2 HBM Crossbars 5.14. Example: 16x16 Crossbar
5.3. Recommended NoC Design Topologies x
5.3.1. 1:1 Connectivity with EMIF and HBM 5.3.2. HBM Crossbars 5.3.3. Connectivity with HPS
6. Debugging the NoC x
6.1. Debugging NoC AXI Transaction Issues 6.2. Debugging NoC Bit Errors 6.3. Debugging NoC Performance Issues
6.3. Debugging NoC Performance Issues x
6.3.1. Measuring Performance with the Signal Tap Logic Analyzer 6.3.2. Measuring Performance with the Performance Monitor 6.3.3. Performance Debug Steps
1. Answers to Top FAQs
2. About This Application Note
3. Component Bandwidth Projections and Limitations
4. Resource Planning for Intel Agilex® 7 M-Series FPGAs
5. Factors Affecting NoC Performance
6. Debugging the NoC
7. Document Revision History of AN 1003: Multi Memory IP System Resource Planning for Intel Agilex® 7 M-Series FPGAs

6.1. Debugging NoC AXI Transaction Issues

If you experience AXI interface failures, such as transactions not completing, or incorrect data being returned, review the following AXI debug recommendations. Logical errors in the RTL typically cause these types of errors.
  1. Capture the interface signals with the Intel® Quartus® Prime software Signal Tap logic analyzer or replicate the issue in simulation.
  2. For a detailed description of the AXI signaling, refer to the High Bandwidth Memory (HBM2E) Interface Intel Agilex® 7 M-Series FPGA IP User Guide.
  3. Use the Signal Tap logic analyzer to verify that the design correctly implements the ready-to-valid valid handshake, as the AXI requirements describe. A common error is incorrect use of the AXI ready-to-valid handshake on all AXI sub-channels.
  4. Ensure that your design correctly specifies addresses for each transaction, per your application requirements and the address map configuration of the NoC initiator. You can verify this transaction in simulation, as Contents of Simulation Registration Include File describes in the Intel Agilex 7 M-Series FPGA Network-on-Chip (NoC) User Guide. If the design issues a transaction address that does not fall into the range of targets mapped by the connections from the initiator, the initiator returns the AXI response DECERR in either BRESP or RRESP.
  5. If using the fabric NoC, the M20Ks implement FIFOs for the read data and you must ensure that they do not overflow. Ensure that RVALID does not remain active without issuing RREADY promptly. Also, the design must meet the read clock frequency requirement of greater than half of the initiator clock frequency.
    Figure 40. Significantly Delayed RREADY Relative to the Assertion of RVALID Risks Overflowing the Read Data FIFOs


  6. In any scenario where you rely on transaction order across different initiators or AxIDs, you must add and validate the synchronization mechanisms for your design. Incorrect data can result if there are transaction sequencing hazards inherent in your design. The AXI specification only requires in-order evaluation of transactions when they are issued by a single initiator and when using a single AxID.
Related Information
Level Two Title