AN 1003: Multi Memory IP System Resource Planning: for Intel Agilex® 7 M-Series FPGAs

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ID 788295
Date 11/22/2023
Public
Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs 2. About This Application Note 3. Component Bandwidth Projections and Limitations 4. Resource Planning for Intel Agilex® 7 M-Series FPGAs 5. Factors Affecting NoC Performance 6. Debugging the NoC 7. Document Revision History of AN 1003: Multi Memory IP System Resource Planning for Intel Agilex® 7 M-Series FPGAs
2. About This Application Note x
2.1. Preliminary Guidelines 2.2. Document Prerequisites 2.3. Terminology for Intel Agilex® 7 M-Series FPGAs
3. Component Bandwidth Projections and Limitations x
3.1. Memory Controller Efficiency 3.2. Hard Memory NoC Bandwidth 3.3. Overall Bandwidth for NoC Systems
3.1. Memory Controller Efficiency x
3.1.1. HBM2E UIB Controller Efficiency 3.1.2. External Memory Interface Controller Efficiency
3.2. Hard Memory NoC Bandwidth x
3.2.1. Horizontal NoC Bandwidth 3.2.2. Initiator NoC Bandwidth 3.2.3. Target NoC Bandwidth 3.2.4. Initiator Target Link Bandwidth
4. Resource Planning for Intel Agilex® 7 M-Series FPGAs x
4.1. Hard Memory NoC Resource Planning Overview 4.2. I/O Bank Blockage 4.3. Planning Avalon® Streaming Utilization 4.4. Planning for Initiator Blockage Impact from GPIO, LVDS SERDES, and PHY Lite Bypass Mode 4.5. Planning NoC PLL and I/O PLL 4.6. Pin Planning for HPS EMIF 4.7. Planning for an External Memory Interface 4.8. Planning for HBM2E 4.9. Planning for the Fabric NoC 4.10. Planning for AXI4-Lite 4.11. Planning NoC and Memory Solution Clocks
4.2. I/O Bank Blockage x
4.2.1. Top Hard Memory NoC 4.2.2. Bottom Hard Memory NoC
4.10. Planning for AXI4-Lite x
4.10.1. Single AXI4 Lite Initiator for Each Horizontal NoC 4.10.2. AXI4-Lite Initiator for HBM2E 4.10.3. AXI4-Lite Initiator for EMIF
4.11. Planning NoC and Memory Solution Clocks x
4.11.1. Clocking without the Fabric NoC 4.11.2. Clocking with the Fabric NoC
5. Factors Affecting NoC Performance x
5.1. Recommended Performance Tuning Procedure 5.2. NoC Initiator and Target Clock Rate 5.3. Recommended NoC Design Topologies 5.4. Traffic Access Pattern and Memory Controller Efficiency 5.5. Traffic Access Pattern Due To Multiple Traffic Flows 5.6. Transaction Size 5.7. Congestion Interaction 5.8. Bandwidth Sharing At Each Switch 5.9. Exceeding NoC Bandwidth Limits 5.10. Maximum Number of Outstanding Transactions 5.11. QoS Priority 5.12. AxID 5.13. Example: 2x2 HBM Crossbars 5.14. Example: 16x16 Crossbar
5.3. Recommended NoC Design Topologies x
5.3.1. 1:1 Connectivity with EMIF and HBM 5.3.2. HBM Crossbars 5.3.3. Connectivity with HPS
6. Debugging the NoC x
6.1. Debugging NoC AXI Transaction Issues 6.2. Debugging NoC Bit Errors 6.3. Debugging NoC Performance Issues
6.3. Debugging NoC Performance Issues x
6.3.1. Measuring Performance with the Signal Tap Logic Analyzer 6.3.2. Measuring Performance with the Performance Monitor 6.3.3. Performance Debug Steps
1. Answers to Top FAQs
2. About This Application Note
3. Component Bandwidth Projections and Limitations
4. Resource Planning for Intel Agilex® 7 M-Series FPGAs
5. Factors Affecting NoC Performance
6. Debugging the NoC
7. Document Revision History of AN 1003: Multi Memory IP System Resource Planning for Intel Agilex® 7 M-Series FPGAs

5.7. Congestion Interaction

A congested connection can impact overlapping connections. For example, a connection that uses a segment of Link 0 that is congested due to memory controller efficiency, can slow down other connections using the same segment. This slow down occurs because NoC packets of the congested connection may cue in the NoC, preventing forward progress of the packets of other connections in the same segment.

Example causes of congested connections include:

  • Exceeding the NoC link bandwidth limits, due to multiple connections attempting to share a segment of a link.
  • Exceeding the throughput capability of a target, due to multiple initiators issuing transactions simultaneously, or due to a slower target frequency than initiator frequency.
  • Issuing a large number of transactions, to a target that cannot handle them as quickly, due to memory controller efficiency.

Congested Connections Overlapping with other Connections Spread Congestion Across the NoC illustrates how congested connections overlapping with other connections can spread congestion across the NoC, reducing the performance of connections that might otherwise perform much better.

In this example:

  • The red connection is the source of congestion, because it has a memory access pattern that leads to low efficiency.
  • The orange connection overlaps with the red connection on Link 0, and its packets on the NoC cannot advance any faster than the packets of the red connection. Therefore, the orange connection becomes congested.
  • The yellow connection does not overlap with the red connection, but it does overlap with the orange connection, which has become congested. Therefore, the yellow connection is now also congested.
  • The green connection is not affected in the scenario in the illustration because the green connection is on a different link than the other connections.
Figure 29. Congested Connections Overlapping with other Connections Spread Congestion Across the NoC


Avoid using overlapping NoC paths between connections that are performance critical, and connections that may have degraded performance. You can avoid these by:

  • Carefully considering which link you place connections on. Refer to Horizontal Bandwidth Considerations in Intel Agilex 7 M-Series FPGA Network-on-Chip (NoC) User Guide.
  • Using the direct connections in the NoC, or placing performance critical connections in separate segments of the NoC from connections where you expect congestion.
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