AN 1003: Multi Memory IP System Resource Planning: for Intel Agilex® 7 M-Series FPGAs

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ID 788295
Date 11/22/2023
Public
Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs 2. About This Application Note 3. Component Bandwidth Projections and Limitations 4. Resource Planning for Intel Agilex® 7 M-Series FPGAs 5. Factors Affecting NoC Performance 6. Debugging the NoC 7. Document Revision History of AN 1003: Multi Memory IP System Resource Planning for Intel Agilex® 7 M-Series FPGAs
2. About This Application Note x
2.1. Preliminary Guidelines 2.2. Document Prerequisites 2.3. Terminology for Intel Agilex® 7 M-Series FPGAs
3. Component Bandwidth Projections and Limitations x
3.1. Memory Controller Efficiency 3.2. Hard Memory NoC Bandwidth 3.3. Overall Bandwidth for NoC Systems
3.1. Memory Controller Efficiency x
3.1.1. HBM2E UIB Controller Efficiency 3.1.2. External Memory Interface Controller Efficiency
3.2. Hard Memory NoC Bandwidth x
3.2.1. Horizontal NoC Bandwidth 3.2.2. Initiator NoC Bandwidth 3.2.3. Target NoC Bandwidth 3.2.4. Initiator Target Link Bandwidth
4. Resource Planning for Intel Agilex® 7 M-Series FPGAs x
4.1. Hard Memory NoC Resource Planning Overview 4.2. I/O Bank Blockage 4.3. Planning Avalon® Streaming Utilization 4.4. Planning for Initiator Blockage Impact from GPIO, LVDS SERDES, and PHY Lite Bypass Mode 4.5. Planning NoC PLL and I/O PLL 4.6. Pin Planning for HPS EMIF 4.7. Planning for an External Memory Interface 4.8. Planning for HBM2E 4.9. Planning for the Fabric NoC 4.10. Planning for AXI4-Lite 4.11. Planning NoC and Memory Solution Clocks
4.2. I/O Bank Blockage x
4.2.1. Top Hard Memory NoC 4.2.2. Bottom Hard Memory NoC
4.10. Planning for AXI4-Lite x
4.10.1. Single AXI4 Lite Initiator for Each Horizontal NoC 4.10.2. AXI4-Lite Initiator for HBM2E 4.10.3. AXI4-Lite Initiator for EMIF
4.11. Planning NoC and Memory Solution Clocks x
4.11.1. Clocking without the Fabric NoC 4.11.2. Clocking with the Fabric NoC
5. Factors Affecting NoC Performance x
5.1. Recommended Performance Tuning Procedure 5.2. NoC Initiator and Target Clock Rate 5.3. Recommended NoC Design Topologies 5.4. Traffic Access Pattern and Memory Controller Efficiency 5.5. Traffic Access Pattern Due To Multiple Traffic Flows 5.6. Transaction Size 5.7. Congestion Interaction 5.8. Bandwidth Sharing At Each Switch 5.9. Exceeding NoC Bandwidth Limits 5.10. Maximum Number of Outstanding Transactions 5.11. QoS Priority 5.12. AxID 5.13. Example: 2x2 HBM Crossbars 5.14. Example: 16x16 Crossbar
5.3. Recommended NoC Design Topologies x
5.3.1. 1:1 Connectivity with EMIF and HBM 5.3.2. HBM Crossbars 5.3.3. Connectivity with HPS
6. Debugging the NoC x
6.1. Debugging NoC AXI Transaction Issues 6.2. Debugging NoC Bit Errors 6.3. Debugging NoC Performance Issues
6.3. Debugging NoC Performance Issues x
6.3.1. Measuring Performance with the Signal Tap Logic Analyzer 6.3.2. Measuring Performance with the Performance Monitor 6.3.3. Performance Debug Steps
1. Answers to Top FAQs
2. About This Application Note
3. Component Bandwidth Projections and Limitations
4. Resource Planning for Intel Agilex® 7 M-Series FPGAs
5. Factors Affecting NoC Performance
6. Debugging the NoC
7. Document Revision History of AN 1003: Multi Memory IP System Resource Planning for Intel Agilex® 7 M-Series FPGAs

4.10.2. AXI4-Lite Initiator for HBM2E

The AXI4-Lite interface for HBM2E is not an essential interface for reading calibration status. However, if your application requires access to configuration and status register information, you must use the AXI4-Lite interface.
The following options are available:
  • Dedicated INIU for AXI4-Lite
  • Shared INIU between AXI4-Lite and AXI4

The High Bandwidth Memory (HBM2E) Interface Intel Agilex® 7 M-Series FPGA IP supports an independent single initiator for the AXI4-Lite interface for all HBM2E AXI4-Lite targets. Alternatively, you can select a shared initiator for mainband AXI4 and sideband AXI4-Lite. AXI4-Lite access for HBM2E is only through the NoC.

Figure 8. Separate AXI4-Lite and AXI4 Initiators


If you want to enable your design with a dedicated AXI4-Lite option, you must instantiate two instances of the NoC Initiator IP. As Separate AXI4-Lite and AXI4 Initiators shows, one instance is for mainband traffic. This instance instantiates 2n initiators, where n is the number of enabled channels. Another instance with a single initiator (iniu_0) is for AXI4-Lite traffic. When you configure the NoC Initiator Intel FPGA IP for AXI4-Lite access, by default, INIU 0 configures for the AXI4-Lite access, which can connect to four sideband targets.

While this arrangement reduces congestion on the initiator and mainband network, the arrangement requires that you use address offset to identify unique AXI4-Lite targets. If your application requires frequent access to AXI4-Lite targets, you may see congestion on this initiator.

Having a shared NoC initiator means that AXI4 and AXI4-Lite can share the INIU. Shared AXI4-Lite and AXI4 Initiator shows the first initiator in the NoC Initiator Intel FPGA IP instance is multiplexed with AXI4 and AXI4-Lite, and with all sixteen channels of HBM2E IP, with four AXI4-Lite targets. You must instantiate four instances of the NoC Initiator Intel FPGA IP, each exposing one AXI4-Lite interface and multiple AXI4 mainband interfaces.

Figure 9. Shared AXI4-Lite and AXI4 Initiator


You can use the other initiators in the same NoC Initiator Intel FPGA IP instance for mainband traffic. The AXI4-Lite interface, and one of the AXI4 interfaces, are multiplexed so that the AXI4 and AXI4-Lite traffic goes through one initiator (INIU 0). In this example, with 16 pseudo channels enabled, and four AXI4-Lite sideband interfaces, you require four instances of the NoC Initiator Intel FPGA IP, where each IP shares the INIU 0 with AXI-Lite and AXI4.

While this shared approach saves an initiator, especially if you have other memory IP in your system, your mainband traffic and sideband traffic share bandwidth on the horizontal NoC and the first instance of the shared initiator. If your system demands frequent access to AXI4-Lite targets, this arrangement can constrain the bandwidth. You may observe a slight increase in core area consumption because of four instances of the soft NoC Initiator IP.

The shared initiator between AXI4 and AXI4-Lite option adds a restriction on fabric NoC usage. If your system requires higher read bandwidth and the use of fabric NoC, you cannot use a shared initiator for mainband and sideband operations. You cannot use the fabric NoC with a shared AXI4-Lite option. However, you can still use the fabric NoC with AXI4-Lite in a dedicated option.

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