AN 1003: Multi Memory IP System Resource Planning: for Intel Agilex® 7 M-Series FPGAs

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ID 788295
Date 11/22/2023
Public
Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs 2. About This Application Note 3. Component Bandwidth Projections and Limitations 4. Resource Planning for Intel Agilex® 7 M-Series FPGAs 5. Factors Affecting NoC Performance 6. Debugging the NoC 7. Document Revision History of AN 1003: Multi Memory IP System Resource Planning for Intel Agilex® 7 M-Series FPGAs
2. About This Application Note x
2.1. Preliminary Guidelines 2.2. Document Prerequisites 2.3. Terminology for Intel Agilex® 7 M-Series FPGAs
3. Component Bandwidth Projections and Limitations x
3.1. Memory Controller Efficiency 3.2. Hard Memory NoC Bandwidth 3.3. Overall Bandwidth for NoC Systems
3.1. Memory Controller Efficiency x
3.1.1. HBM2E UIB Controller Efficiency 3.1.2. External Memory Interface Controller Efficiency
3.2. Hard Memory NoC Bandwidth x
3.2.1. Horizontal NoC Bandwidth 3.2.2. Initiator NoC Bandwidth 3.2.3. Target NoC Bandwidth 3.2.4. Initiator Target Link Bandwidth
4. Resource Planning for Intel Agilex® 7 M-Series FPGAs x
4.1. Hard Memory NoC Resource Planning Overview 4.2. I/O Bank Blockage 4.3. Planning Avalon® Streaming Utilization 4.4. Planning for Initiator Blockage Impact from GPIO, LVDS SERDES, and PHY Lite Bypass Mode 4.5. Planning NoC PLL and I/O PLL 4.6. Pin Planning for HPS EMIF 4.7. Planning for an External Memory Interface 4.8. Planning for HBM2E 4.9. Planning for the Fabric NoC 4.10. Planning for AXI4-Lite 4.11. Planning NoC and Memory Solution Clocks
4.2. I/O Bank Blockage x
4.2.1. Top Hard Memory NoC 4.2.2. Bottom Hard Memory NoC
4.10. Planning for AXI4-Lite x
4.10.1. Single AXI4 Lite Initiator for Each Horizontal NoC 4.10.2. AXI4-Lite Initiator for HBM2E 4.10.3. AXI4-Lite Initiator for EMIF
4.11. Planning NoC and Memory Solution Clocks x
4.11.1. Clocking without the Fabric NoC 4.11.2. Clocking with the Fabric NoC
5. Factors Affecting NoC Performance x
5.1. Recommended Performance Tuning Procedure 5.2. NoC Initiator and Target Clock Rate 5.3. Recommended NoC Design Topologies 5.4. Traffic Access Pattern and Memory Controller Efficiency 5.5. Traffic Access Pattern Due To Multiple Traffic Flows 5.6. Transaction Size 5.7. Congestion Interaction 5.8. Bandwidth Sharing At Each Switch 5.9. Exceeding NoC Bandwidth Limits 5.10. Maximum Number of Outstanding Transactions 5.11. QoS Priority 5.12. AxID 5.13. Example: 2x2 HBM Crossbars 5.14. Example: 16x16 Crossbar
5.3. Recommended NoC Design Topologies x
5.3.1. 1:1 Connectivity with EMIF and HBM 5.3.2. HBM Crossbars 5.3.3. Connectivity with HPS
6. Debugging the NoC x
6.1. Debugging NoC AXI Transaction Issues 6.2. Debugging NoC Bit Errors 6.3. Debugging NoC Performance Issues
6.3. Debugging NoC Performance Issues x
6.3.1. Measuring Performance with the Signal Tap Logic Analyzer 6.3.2. Measuring Performance with the Performance Monitor 6.3.3. Performance Debug Steps
1. Answers to Top FAQs
2. About This Application Note
3. Component Bandwidth Projections and Limitations
4. Resource Planning for Intel Agilex® 7 M-Series FPGAs
5. Factors Affecting NoC Performance
6. Debugging the NoC
7. Document Revision History of AN 1003: Multi Memory IP System Resource Planning for Intel Agilex® 7 M-Series FPGAs

3.2.2. Initiator NoC Bandwidth

NoC initiators are the bridges between the AXI4 manager in user logic and the hard memory NoC. The hard memory NoC along the top edge of the device contains 20 NoC initiators facing the FPGA fabric and two NoC initiators that interact with the HPS. The hard memory NoC along the bottom edge of the device contains 22 NoC initiators facing the FPGA fabric.

There is an additional service network running parallel to the main switch network within each hard memory NoC. This service network connects the NoC SSM and the HPS AXI4-Lite initiator to AXI4-Lite targets.

Note: The top edge of the device contains two AXI4 initiators, and one AXI4-Lite initiator on the HPS multi-port front end (MPFE) side.

Initiator Frequency across Device Speed Grade shows the maximum frequencies of a NoC initiator in a design as a function of the device speed grade. Complex and congested designs may not achieve these frequencies, and the Intel® Quartus® Prime software may report warnings during compilation.

Table 5.  Initiator Frequency Across Device Speed Grade
Device Speed Grade NoC Initiator Frequency (MHz)
-1 <=660
-2 <=630
-3 <=450

You use the NoC Initiator Intel FPGA IP to configure the AXI4 or AXI4-Lite interfaces between AXI4 managers in your logic and the hard memory NoC. Configuring the NoC Initiator Intel FPGA IP exposes several clocking scenarios, as Planning NoC and Memory Solution Clocks describes. During compilation, the Fitter maps these interfaces to NoC initiator bridges in the hard memory NoC.

The number of NoC initiators in your design depends on the memory bandwidth requirements of the application you are designing. Calculate the bandwidth that an individual NoC initiator can support by multiplying the width of its data bus by the clock frequency of the logic driving the NoC initiator. Higher operating frequencies may require fewer NoC initiators but can encounter more difficulty when closing timing.



Where:

On a -2 speed grade device, with an initiator running at 630MHz, you can expect to achieve a maximum bandwidth of 20.16GBps.

For more information on bandwidth considerations, refer to Initiator and Target Bandwidth Considerations in Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide.

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