AN 1003: Multi Memory IP System Resource Planning: for Intel Agilex® 7 M-Series FPGAs

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ID 788295
Date 11/22/2023
Public
Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs 2. About This Application Note 3. Component Bandwidth Projections and Limitations 4. Resource Planning for Intel Agilex® 7 M-Series FPGAs 5. Factors Affecting NoC Performance 6. Debugging the NoC 7. Document Revision History of AN 1003: Multi Memory IP System Resource Planning for Intel Agilex® 7 M-Series FPGAs
2. About This Application Note x
2.1. Preliminary Guidelines 2.2. Document Prerequisites 2.3. Terminology for Intel Agilex® 7 M-Series FPGAs
3. Component Bandwidth Projections and Limitations x
3.1. Memory Controller Efficiency 3.2. Hard Memory NoC Bandwidth 3.3. Overall Bandwidth for NoC Systems
3.1. Memory Controller Efficiency x
3.1.1. HBM2E UIB Controller Efficiency 3.1.2. External Memory Interface Controller Efficiency
3.2. Hard Memory NoC Bandwidth x
3.2.1. Horizontal NoC Bandwidth 3.2.2. Initiator NoC Bandwidth 3.2.3. Target NoC Bandwidth 3.2.4. Initiator Target Link Bandwidth
4. Resource Planning for Intel Agilex® 7 M-Series FPGAs x
4.1. Hard Memory NoC Resource Planning Overview 4.2. I/O Bank Blockage 4.3. Planning Avalon® Streaming Utilization 4.4. Planning for Initiator Blockage Impact from GPIO, LVDS SERDES, and PHY Lite Bypass Mode 4.5. Planning NoC PLL and I/O PLL 4.6. Pin Planning for HPS EMIF 4.7. Planning for an External Memory Interface 4.8. Planning for HBM2E 4.9. Planning for the Fabric NoC 4.10. Planning for AXI4-Lite 4.11. Planning NoC and Memory Solution Clocks
4.2. I/O Bank Blockage x
4.2.1. Top Hard Memory NoC 4.2.2. Bottom Hard Memory NoC
4.10. Planning for AXI4-Lite x
4.10.1. Single AXI4 Lite Initiator for Each Horizontal NoC 4.10.2. AXI4-Lite Initiator for HBM2E 4.10.3. AXI4-Lite Initiator for EMIF
4.11. Planning NoC and Memory Solution Clocks x
4.11.1. Clocking without the Fabric NoC 4.11.2. Clocking with the Fabric NoC
5. Factors Affecting NoC Performance x
5.1. Recommended Performance Tuning Procedure 5.2. NoC Initiator and Target Clock Rate 5.3. Recommended NoC Design Topologies 5.4. Traffic Access Pattern and Memory Controller Efficiency 5.5. Traffic Access Pattern Due To Multiple Traffic Flows 5.6. Transaction Size 5.7. Congestion Interaction 5.8. Bandwidth Sharing At Each Switch 5.9. Exceeding NoC Bandwidth Limits 5.10. Maximum Number of Outstanding Transactions 5.11. QoS Priority 5.12. AxID 5.13. Example: 2x2 HBM Crossbars 5.14. Example: 16x16 Crossbar
5.3. Recommended NoC Design Topologies x
5.3.1. 1:1 Connectivity with EMIF and HBM 5.3.2. HBM Crossbars 5.3.3. Connectivity with HPS
6. Debugging the NoC x
6.1. Debugging NoC AXI Transaction Issues 6.2. Debugging NoC Bit Errors 6.3. Debugging NoC Performance Issues
6.3. Debugging NoC Performance Issues x
6.3.1. Measuring Performance with the Signal Tap Logic Analyzer 6.3.2. Measuring Performance with the Performance Monitor 6.3.3. Performance Debug Steps
1. Answers to Top FAQs
2. About This Application Note
3. Component Bandwidth Projections and Limitations
4. Resource Planning for Intel Agilex® 7 M-Series FPGAs
5. Factors Affecting NoC Performance
6. Debugging the NoC
7. Document Revision History of AN 1003: Multi Memory IP System Resource Planning for Intel Agilex® 7 M-Series FPGAs

4.10. Planning for AXI4-Lite

The Intel Agilex® 7 M-Series FPGA hard memory NoC supports a lightweight AXI4-Lite interface to access the control and status registers of HBM2E and EMIF.

AXI4-Lite is a lightweight interface compared to AXI4, meaning that it has lower performance and higher latency without bursting support and other features. You use this interface to enable access to control and status registers, such as thermal status register (only for HBM2E) and ECC error counters register for both UIB and GPIO-B.

The NoC support for AXI4-Lite interfaces includes the following:

  • Six AXI4-Lite targets on the UIB side
  • One AXI4-Lite target on each GPIO-B block side
  • One AXI4-Lite initiator on the HPS side
  • One AXI4-Lite initiator in the NoC SSM to connect to the service network

The NoC Initiator Intel FPGA IP enables you to configure AXI4 or AXI4-Lite interfaces between AXI4 managers in your logic and the hard memory NoC. Through this IP, you can select a separate or shared initiator configuration for AXI4-Lite sideband and AXI4 mainband operation. You can configure the NoC Initiator Intel FPGA IP to share the NoC initiator bridge between an AXI4 interface and up to four AXI4-Lite interfaces, unless you are using the fabric NoC on the same bridge.

AXI4-Lite transactions from fabric-facing initiators first route along the main switch network to the NoC SSM, acting as a bridge and transferring these requests onto the service network. The service network connects to the AXI4-Lite targets. The AXI4-Lite initiator in the HPS MPFE connects directly to the AXI4-Lite targets through the service network.

AXI4-Lite is the required interface for EMIF to read the calibration status before launching the user traffic. AXI4-Lite usage with HBM2E is optional and provides fine grained information on temperature readings.

For ease of use, and to avoid sharing of sideband bandwidth with main data traffic, you can choose to use a single, dedicated initiator to drive the sideband for all memories on the same side of the hard memory NoC. However, when you have a larger requirement for GPIO or LVDS, or have multiple EMIFs, or require full bandwidth on HBM2E with 16 initiators, sparing an extra initiator for dedicated side band operations becomes challenging.

This section explains creative options and caveats necessary to plan AXI4-Lite usage with minimum initiators.

For additional architecture details, refer to NoC Initiator Intel FPGA IP in Intel Agilex 7 M-Series FPGA Network-on-Chip (NoC) User Guide


Section Content
Single AXI4 Lite Initiator for Each Horizontal NoC
AXI4-Lite Initiator for HBM2E
AXI4-Lite Initiator for EMIF

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