AN 1003: Multi Memory IP System Resource Planning: for Intel Agilex® 7 M-Series FPGAs

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ID 788295
Date 11/22/2023
Public
Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs 2. About This Application Note 3. Component Bandwidth Projections and Limitations 4. Resource Planning for Intel Agilex® 7 M-Series FPGAs 5. Factors Affecting NoC Performance 6. Debugging the NoC 7. Document Revision History of AN 1003: Multi Memory IP System Resource Planning for Intel Agilex® 7 M-Series FPGAs
2. About This Application Note x
2.1. Preliminary Guidelines 2.2. Document Prerequisites 2.3. Terminology for Intel Agilex® 7 M-Series FPGAs
3. Component Bandwidth Projections and Limitations x
3.1. Memory Controller Efficiency 3.2. Hard Memory NoC Bandwidth 3.3. Overall Bandwidth for NoC Systems
3.1. Memory Controller Efficiency x
3.1.1. HBM2E UIB Controller Efficiency 3.1.2. External Memory Interface Controller Efficiency
3.2. Hard Memory NoC Bandwidth x
3.2.1. Horizontal NoC Bandwidth 3.2.2. Initiator NoC Bandwidth 3.2.3. Target NoC Bandwidth 3.2.4. Initiator Target Link Bandwidth
4. Resource Planning for Intel Agilex® 7 M-Series FPGAs x
4.1. Hard Memory NoC Resource Planning Overview 4.2. I/O Bank Blockage 4.3. Planning Avalon® Streaming Utilization 4.4. Planning for Initiator Blockage Impact from GPIO, LVDS SERDES, and PHY Lite Bypass Mode 4.5. Planning NoC PLL and I/O PLL 4.6. Pin Planning for HPS EMIF 4.7. Planning for an External Memory Interface 4.8. Planning for HBM2E 4.9. Planning for the Fabric NoC 4.10. Planning for AXI4-Lite 4.11. Planning NoC and Memory Solution Clocks
4.2. I/O Bank Blockage x
4.2.1. Top Hard Memory NoC 4.2.2. Bottom Hard Memory NoC
4.10. Planning for AXI4-Lite x
4.10.1. Single AXI4 Lite Initiator for Each Horizontal NoC 4.10.2. AXI4-Lite Initiator for HBM2E 4.10.3. AXI4-Lite Initiator for EMIF
4.11. Planning NoC and Memory Solution Clocks x
4.11.1. Clocking without the Fabric NoC 4.11.2. Clocking with the Fabric NoC
5. Factors Affecting NoC Performance x
5.1. Recommended Performance Tuning Procedure 5.2. NoC Initiator and Target Clock Rate 5.3. Recommended NoC Design Topologies 5.4. Traffic Access Pattern and Memory Controller Efficiency 5.5. Traffic Access Pattern Due To Multiple Traffic Flows 5.6. Transaction Size 5.7. Congestion Interaction 5.8. Bandwidth Sharing At Each Switch 5.9. Exceeding NoC Bandwidth Limits 5.10. Maximum Number of Outstanding Transactions 5.11. QoS Priority 5.12. AxID 5.13. Example: 2x2 HBM Crossbars 5.14. Example: 16x16 Crossbar
5.3. Recommended NoC Design Topologies x
5.3.1. 1:1 Connectivity with EMIF and HBM 5.3.2. HBM Crossbars 5.3.3. Connectivity with HPS
6. Debugging the NoC x
6.1. Debugging NoC AXI Transaction Issues 6.2. Debugging NoC Bit Errors 6.3. Debugging NoC Performance Issues
6.3. Debugging NoC Performance Issues x
6.3.1. Measuring Performance with the Signal Tap Logic Analyzer 6.3.2. Measuring Performance with the Performance Monitor 6.3.3. Performance Debug Steps
1. Answers to Top FAQs
2. About This Application Note
3. Component Bandwidth Projections and Limitations
4. Resource Planning for Intel Agilex® 7 M-Series FPGAs
5. Factors Affecting NoC Performance
6. Debugging the NoC
7. Document Revision History of AN 1003: Multi Memory IP System Resource Planning for Intel Agilex® 7 M-Series FPGAs

4.1. Hard Memory NoC Resource Planning Overview

This section's explanation of resource planning focuses on only the total available initiators and their relationship with the I/O bank and the UIB.

Top Hard Memory NoC and Bottom Hard Memory NoC show the arrangement of elements in the top and the bottom hard memory NoC. Every NoC initiator can communicate to every target on the same NoC side. This allows you the flexibility to implement a fully hardened crossbar.

The switches in the NoC route the requests and responses between initiators and targets using an AXI4 protocol. Each HBM2E stack communicates with its NoC via its UIB. Off-chip memories (such as DDR4 or DDR5) communicate with the NoC via the GPIO-B I/O bank subsystems. The NoC routes data from its source to its destination via a network that consists of switches (routers), interconnect links, initiators (INIU), and targets (TNIU).

Because of routing resource limitations, functions implemented in each I/O bank can block the use of certain initiator bridges. Conversely, using certain initiator bridges can block the use of I/O banks. In Top Hard Memory NoC and Bottom Hard Memory NoC, the color coding on each byte lane of the I/O bank shows matching blockage on the initiator under an I/O bank.

Note: The figures in this section do not depict AXI4 targets (TNIU) nor AXI4-Lite targets (TNIU Lite) for simplicity and focus on design impact elements. Targets are the bridges between AXI4 subordinate IP (EMIF or HBM2E) in the periphery and the hard memory NoC.

For more architectural details on various elements, refer to the following:

  • For more details on the NoC architecture, refer to Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide.
  • For more details on the I/O land, sub-I/O bank, and other architecture, refer to External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP User Guide .
  • For more details on the HBM2E architecture and IP, refer to the High Bandwidth Memory (HBM2E) Interface Intel Agilex® 7 FPGA IP User Guide
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