5.3.1. 1G/2.5G/5G/10G Multirate PHY
This topic lists the byte offsets of the 1G/2.5G/5G/10G Multirate variant registers for Agilex™ 7 (F-Tile) devices.
Register Map
You can access the 32-bit configuration registers via the Avalon® memory-mapped interface.
Address Range | Usage | Register Width | Configuration |
---|---|---|---|
0x400 : 0x43F |
USXGMII | 32 | 10M/100M/1G/2.5G/5G/10G (USXGMII) |
Register Definitions
- Do not write to reserved or undefined registers.
- When writing to the registers, perform read-modify-write operation to ensure that reserved or undefined register bits are not overwritten.
Word Offset | Name | Description | Access | HW Reset Value |
---|---|---|---|---|
0x400 | usxgmii_control | Control Register | — | — |
Bit [0]: USXGMII_ENA:
|
RW | 0 | ||
Bit [1]: USXGMII_AN_ENA is used when USXGMII_ENA is set to 1:
|
RW | 1 | ||
Bit [4:2]: USXGMII_SPEED is the operating speed of the PHY in USXGMII mode and USE_USXGMII_AN is set to 0.
|
RW | 0 | ||
Bit [8:5]: Reserved | — | — | ||
Bit [9]: RESTART_AUTO_NEGOTIATION Write 1 to restart Auto-Negotiation sequence The bit is cleared by hardware when Auto-Negotiation is restarted. |
RWC | 0 | ||
Bit [31:10]: Reserved | — | — | ||
0x401 | usxgmii_status | Status Register | — | — |
Bit [1:0]: Reserved | — | — | ||
Bit [2]: LINK_STATUS indicates link status for USXGMII all speeds
|
RO | 0 | ||
Bit [4:3]: Reserved | — | — | ||
Bit [5]: AUTO_NEGOTIATION_COMPLETE A value of 1 indicates the Auto-Negotiation process is completed. |
RO | 0 | ||
Bit [31:6]: Reserved | — | — | ||
0x402:0x404 | Reserved | — | — | — |
0x405 | usxgmii_partner_ability | Device abilities advertised to the link partner during Auto-Negotiation | — | — |
Bit [6:0]: Reserved | — | — | ||
Bit [7]: EEE_CLOCK_STOP_CAPABILITY
Indicates whether or not energy efficient Ethernet (EEE) clock stop is supported.
|
RO | 0 | ||
Bit [8]: EEE_CAPABILITY
Indicates whether or not EEE is supported.
|
RO | 0 | ||
Bit [11:9]: SPEED
|
RO | 0 | ||
Bit [12]: DUPLEX
Indicates the duplex mode.
|
RO | 0 | ||
Bit [13]: Reserved | — | — | ||
Bit [14]: ACKNOWLEDGE A value of 1 indicates that the device has received three consecutive matching ability values from its link partner. |
RO | 0 | ||
Bit [15]: LINK
Indicates the link status.
|
RO | 0 | ||
Bit [31:16]: Reserved | — | — | ||
0x406:0x411 | Reserved | — | — | — |
0x412 | usxgmii_link_timer | Auto-Negotiation link timer. Sets the link timer value in bit [19:14] from 0 to 2 ms in approximately 0.05-ms steps. You must program the link timer to ensure that it matches the link timer value of the external NBASE-T PHY IP. The reset value sets the link timer to approximately 1.6 ms. Bits [13:0] are reserved and always set to 0. |
[19:14]: RW [13:0]: RO |
[19:14]: 1F [13:0]: 0 |
0x413:0x41F | Reserved | — | — | — |
0x420 | ptp_dl | Bit [0]: tx_measure_valid
Indicates whether the TX deterministic latency measurement values are valid.
|
RO | 0x0 |
Bit [1]: rx_measure_valid
Indicates whether the RX deterministic latency measurement values are valid.
|
RO | 0x0 | ||
Bit [2]: tx_dl_reset
TX Deterministic Latency (DL) soft reset. Provides a soft reset to the TX DL block.
Note: This is not a self-clearing reset.
|
RW | 0x0 | ||
Bit [3]: rx_dl_reset
RX Deterministic Latency (DL) soft reset. Provides a soft reset to the RX DL block.
Note: This is not a self-clearing reset.
|
RW | 0x0 | ||
0x421 | ptp_dl_tx | Bit [20:0]: TX Datapath Latency.
Provides the TX datapath deterministic latency values measured in sampling_clk cycles. Fixed point format Q13.8.
tx_measure_valid (bit 0 of register 0x420) must be asserted before taking the measurement. |
RO | 0x0 |
0x422 | ptp_dl_rx | Bit [20:0]: RX Datapath Latency.
Provides the RX datapath deterministic latency values measured in sampling_clk cycles. Fixed point format Q13.8.
rx_measure_valid (bit 0 of register 0x420) must be asserted before taking the measurement. |
RO | 0x0 |