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1. Introduction
2. Necessity of Error Correction
3. FEC Selection
4. FEC in Intel® Stratix® 10 H-Tile Devices
5. FEC in Intel® Stratix® 10 E-Tile Devices
6. FEC Implementation Using the E-Tile Channel Placement Tool
7. FEC in Practical Application
8. Hardware Results
9. Document Revision History for AN 846: Intel® Stratix® 10 Forward Error Correction
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8.2. Test Setup
The test configuration included:
- An Intel® Stratix® 10 TX signal integrity development kit board using the E-Tile device
- FCI backplane (Megtron 6 material)
- Variable ISI box
The FCI backplane is connected to the E-Tile device on one lane, starting with 28 dB loss (error free even without FEC). Attenuation is increased on only one channel using the variable ISI box. This provides fine control over the insertion loss.
Figure 30. Test Setup Board
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