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1. Introduction
2. Necessity of Error Correction
3. FEC Selection
4. FEC in Intel® Stratix® 10 H-Tile Devices
5. FEC in Intel® Stratix® 10 E-Tile Devices
6. FEC Implementation Using the E-Tile Channel Placement Tool
7. FEC in Practical Application
8. Hardware Results
9. Document Revision History for AN 846: Intel® Stratix® 10 Forward Error Correction
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6. FEC Implementation Using the E-Tile Channel Placement Tool
The E-Tile Channel Placement Tool allows you to swiftly plan protocol placements in the product prior to reading comprehensive documentation and implementing designs in the Intel® Quartus® Prime software.
The Excel-based E-Tile Channel Placement Tool, supplemented with Instruction, Legend, Revision and Protocols tabs, is self-sustaining, and available for download.
Figure 22. Fractured ModeEach lane has its own FEC block. This example uses 25GbE EHIP_LANE MAC + PCS with RS (528, 514).
Figure 23. Aggregate ModeFour lanes with FEC blocks bundled together. Examples include:
- 100GbE EHIP_CORE (25G * 4) MAC + PCS with RS (528, 514)
- 100GbE EHIP_CORE (50G * 2) MAC + PCS with RS (544, 514)
Figure 24. E-Tile Channel Placement Tool with 4 * 25GbE with RS-FEC (NRZ)In this configuration, RS-FEC is in fractured mode.
Figure 25. E-Tile Channel Placement Tool with 100GBASE-KR4/CR4 (NRZ)In this configuration, RS-FEC is in aggregate mode.
Figure 26. E-Tile Channel Placement Tool with 100GBASE-KR2/CR2 (PAM4)In this configuration, RS-FEC is in aggregate mode.
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