AN 846: Intel® Stratix® 10 Forward Error Correction

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ID 683805
Date 7/02/2018
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Necessity of Error Correction 3. FEC Selection 4. FEC in Intel® Stratix® 10 H-Tile Devices 5. FEC in Intel® Stratix® 10 E-Tile Devices 6. FEC Implementation Using the E-Tile Channel Placement Tool 7. FEC in Practical Application 8. Hardware Results 9. Document Revision History for AN 846: Intel® Stratix® 10 Forward Error Correction
2. Necessity of Error Correction x
2.1. Solutions to Transmission Errors 2.2. Error Correction Codes 2.3. What is FEC?
2.1. Solutions to Transmission Errors x
2.1.1. Parity and Cyclic Redundancy Check 2.1.2. Error Correction Code (ECC) Block Coding
2.3. What is FEC? x
2.3.1. FEC Definitions
3. FEC Selection x
3.1. Key Considerations when Choosing a FEC
4. FEC in Intel® Stratix® 10 H-Tile Devices x
4.1. Fire Code (802.3ap, 10GBASE-KR)
4.1. Fire Code (802.3ap, 10GBASE-KR) x
4.1.1. FEC Block Format 4.1.2. FEC Block Composition 4.1.3. FEC Sublayer for BASE-R PHYs 4.1.4. L-Tile/H-Tile Implementation
4.1.4. L-Tile/H-Tile Implementation x
4.1.4.1. Transcode Encoder 4.1.4.2. KR FEC Encoder 4.1.4.3. KR FEC Scrambler 4.1.4.4. KR FEC TX Gearbox 4.1.4.5. KR FEC RX Gearbox 4.1.4.6. Transcode Decoder
5. FEC in Intel® Stratix® 10 E-Tile Devices x
5.1. Types of RS-FEC 5.2. 100GBASE-KR4 5.3. 100GBASE-KP4 5.4. FEC Decoders 5.5. Specifications 5.6. Functions Within the RS-FEC Sublayer
5.1. Types of RS-FEC x
5.1.1. RS (528, 514, t = 7, m = 10) 5.1.2. RS (544, 514, t = 15, m = 10) 5.1.3. Supported RS-FEC Modes in E-Tile Devices
5.2. 100GBASE-KR4 x
5.2.1. 100GBASE-KR4 Mapping (IEEE802.3bj Clause 91)
5.3. 100GBASE-KP4 x
5.3.1. 100GBASE-KP4 Mapping (IEEE802.3bj Clause 91)
5.6. Functions Within the RS-FEC Sublayer x
5.6.1. Lane Block Synchronization 5.6.2. Alignment Lock and Deskew 5.6.3. Lane Re-order 5.6.4. Alignment Marker Removal 5.6.5. 64B/66B to 256B/257B Transcoder
7. FEC in Practical Application x
7.1. Datacenter Applications Scenario
8. Hardware Results x
8.1. Test Design 8.2. Test Setup 8.3. Insertion Loss Plots 8.4. FEC Statistics Tool 8.5. Hardware Data 8.6. Comparison to the Specification 8.7. References
1. Introduction
2. Necessity of Error Correction
3. FEC Selection
4. FEC in Intel® Stratix® 10 H-Tile Devices
5. FEC in Intel® Stratix® 10 E-Tile Devices
6. FEC Implementation Using the E-Tile Channel Placement Tool
7. FEC in Practical Application
8. Hardware Results
9. Document Revision History for AN 846: Intel® Stratix® 10 Forward Error Correction

1. Introduction

This application note explains forward error correction (FEC) theory and the Intel® Stratix® 10 device family's FEC capabilities.

Forward error correction is a powerful method of correcting errors that can occur on a serial link. Although very useful, it can be costly in both area and power when implemented in soft logic. For this reason, E-Tile and H-Tile devices provide hardened FEC blocks to address many important applications, such as:

  • 10 Gigabit Ethernet (GbE) (H-Tile)
  • 25GbE (E-Tile)
  • 100GbE (E-Tile)
  • 24.3 Gbps Common Public Radio Interface (CPRI) (E-Tile)
  • 128 gigabit fibre channel (GFC) (E-Tile)
Table 1.  FEC Type Comparison by Transceiver Tile
H-Tile E-Tile
Fire Code—NRZ Reed Solomon (RS) Code—NRZ Reed Solomon (RS) Code—PAM4
  • RS (2112, 2080) (in bits)
  • Binary code (operates on bits)
  • Lower gain (2-2.5 dB)
  • Moderate burst correction
  • Supports 802.3ap, 10GBASE-KR
  • RS-FEC: RS (528, 514, 7 ,10) (in symbols)
  • Non-binary code
  • Good gain (5-5.5 dB)
  • Corrects both random and burst errors
  • Supports 802.3bj, 100GBASE-KR4
  • KP-FEC: RS (544, 514, 15, 10) (in symbols)
  • Non-binary code
  • Very good gain (6-6.5 dB)
  • Corrects both random and burst errors
  • Supports 802.3bj, CEI 56G, 100GBASE-KP2
Level Two Title