Visible to Intel only — GUID: kix1525716411648
Ixiasoft
1. Introduction
2. Necessity of Error Correction
3. FEC Selection
4. FEC in Intel® Stratix® 10 H-Tile Devices
5. FEC in Intel® Stratix® 10 E-Tile Devices
6. FEC Implementation Using the E-Tile Channel Placement Tool
7. FEC in Practical Application
8. Hardware Results
9. Document Revision History for AN 846: Intel® Stratix® 10 Forward Error Correction
Visible to Intel only — GUID: kix1525716411648
Ixiasoft
7.1. Datacenter Applications Scenario
Datacenters are one of the leading application spaces for next generation Ethernet.
Consider a typical datacenter topology.
Figure 27. Typical Datacenter Network Topology
The interconnection between the spine switches and the lead switches is a 10G/40G/100G backplane.
25GbE is a proposed standard for Ethernet connectivity in a datacenter application space, and takes advantage of the technology defined for 100GbE as four 25 Gbps lanes running on four fibers or copper pairs.
Figure 28. Switch-to-Switch Connection Using 4 x 25GbEThe PHY layer of this connection between one switch to another includes the FEC layer.