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1. Introduction
2. Necessity of Error Correction
3. FEC Selection
4. FEC in Intel® Stratix® 10 H-Tile Devices
5. FEC in Intel® Stratix® 10 E-Tile Devices
6. FEC Implementation Using the E-Tile Channel Placement Tool
7. FEC in Practical Application
8. Hardware Results
9. Document Revision History for AN 846: Intel® Stratix® 10 Forward Error Correction
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5.6.2. Alignment Lock and Deskew
Once the RS-FEC transmit function achieves block lock on a PCS lane, it begins obtaining alignment marker lock.
Alignment marker lock identifies the PCS lane number received on a particular lane of the service interface. After alignment marker lock is achieved on all 20 lanes, all inter-lane skew is removed. The RS-FEC transmit function supports a maximum skew of 49 ns between PCS lanes, and a maximum skew variation of 400 ps.