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1. Introduction
2. Necessity of Error Correction
3. FEC Selection
4. FEC in Intel® Stratix® 10 H-Tile Devices
5. FEC in Intel® Stratix® 10 E-Tile Devices
6. FEC Implementation Using the E-Tile Channel Placement Tool
7. FEC in Practical Application
8. Hardware Results
9. Document Revision History for AN 846: Intel® Stratix® 10 Forward Error Correction
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5.3.1. 100GBASE-KP4 Mapping (IEEE802.3bj Clause 91)
Figure 18. 100GBASE-KP4 Mapping
- RS (544, 514, 15, 10) FEC
- 26.5625 Gbps
- 3.03% rate expansion
- Data is stripped per symbol across four lanes
RS(544, 514) requires additional room to accommodate 5440 bits instead of 5280 bits. After transcoding, it must additionally make room for approximately 3% more bits of overhead. The precise overhead is calculated as 1/33; new rate = old rate * 34/33. This result is overspeed for PAM4. For example:
- Payload data rate = 50 Gbps
- Encoding it to 66b encoding: 50*66/64 = 51.5625 Gbps
- Adding FEC expansion: 51.5625*(34/33) = 53.125 Gbps
Intel® Stratix® 10TX devices do not support the 100GBASE-KP4 physical medium dependent (PMD).