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1. Introduction
2. Necessity of Error Correction
3. FEC Selection
4. FEC in Intel® Stratix® 10 H-Tile Devices
5. FEC in Intel® Stratix® 10 E-Tile Devices
6. FEC Implementation Using the E-Tile Channel Placement Tool
7. FEC in Practical Application
8. Hardware Results
9. Document Revision History for AN 846: Intel® Stratix® 10 Forward Error Correction
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8.3. Insertion Loss Plots
Figure 31. M6 Backplane, OIF Stressed SlotNyquist: 12.8 GHz, Insertion Loss: 23 dB
Figure 32. Variable ISI Box Insertion LossNyquist: 12.8 GHz. Each percentage plot corresponds to the setting in the variable ISI box. This graph explains how the variable ISI box setting maps to insertion loss.